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Recent content by bellbell

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    Value change dump file

    fichier vcd dump If you are using Signalscan to watch the waveform, VCD file is huge not convenient at all--each time you have to convert a VCD file to db file. Try to use "simulation history manager" instead of VCD, which is much more favorable.
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    VHDL and Verilog which one you use more often?

    I use verilog. And my friends in Irvine, California, and friends in San Jose, California are using Verilog.
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    An extremely good course on ASIC Design

    **broken link removed** From this web site, you can find toturials on ASIC design flow, on state-of-the-art ASIC design tools (Ambit BuildGates, SOC Encounter, and etc.). Comprehensive course materials and labs. Check it out!
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    about soft radio - any materials?

    Re: about soft radio From my point of view, software radio is not realistic at all. Since it requires high speed ADC, maybe in RF. That's the reason that the software radio has been proposed for years but no real applications till now.
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    Anyone has FFT Benchmarks on power consumptions?

    I search the internet but I can only find FFT benchmarks for speed and etc, but I couldn't find any benchmarks for power consumption. Anyone can help? Thanks a lot.
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    how do you use the virtuoso xl in your design?

    To call Hspice in cds, you don't need the hspice view. All you need is to choode "hspiceS" as simulator and specify the model libraries. Then you can just follow the same procedures as you run Spectre in cds.
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    What is better for a digital designer: Cadence or Synopsis?

    cadence vs synopsis I think it would be better to have both tools. As a digital IC designer, you may want to use Cadence's schematic capture tool, Verilog simulator, and its layout tools like SE; you may also want to use Synopsys for synthesis and power estimation and etc.
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    VHDL vs Verilog which more popular?

    From my experience, Verilog is used more widely in industry, while VHDL is used more widely in schools and small companies.

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