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hello
i read that cascode structure has advantages on high reverse isolation and reducing the effect of Cgd
plz explain them, how are they possible??
can anyone give me some material on this?
thank you
deepak
hello
i need the specifications of individual components of a bluetooth receiver like noise figure, power gain, IIP3 etc of filter, LNA, mixer.
plz reply soon, i need to include them in my thesis
thank you
deepak
Im doing synthesis in Synopsys DC using its library (default) and i want to go for soc encounter for place and route should the tech libraries should be same
Re: LNA post layout
hi
thanks for your reply
my output matching S22 is fine...but input matching S11 is too bad..is this the inductor problem???
i am using the inductors provided by UMC.
i designed an inductively degenerated LNA for single frequency...ckt simulation is fine..i drew its layout...DRC,LVS are fine..but post layout is too bad
the input impedance is only 2 ohm...instead of 50ohm...what should i do?? plz help me
deepak
i am new to switched capacitor filter theory
i simulated one elliptical LPF with 1k pass band which is given the hspice manual
In the response of the filter , the amplitude is changing with time for a particular frequency
i think for a filter the amplitude should not change with time for a...
Re: error in simulating Low Noise Amplifier using Spectre (h
net25 is the error it is showing
i did not write it in the ckt file, it is a schematic simulation
i am simulating an LNA with Spectre, it is showing the following the following error
Matrix is singular ( Detected at net 25)
ciruit has a non singular solution
error diagonal found in jacobian at " net 2g" and "net 25"
i am unable to find the net 25, even it is giving error is netlist...
Where can i find the RF voltage source in spectre??
i want to simulate the S-Parameters of an LNA
in analoglib , there are voltage sources but we cant give port numbers to them, i read from manual that only RF voltage sources can be given some port numbeirs
i think port numbers are compulsory...
capacitors 10pf
thanks for ur reply
i am doing SDL( schematic driven layout) of an mim capacitor.....but the capacitor layout is huge with w=100um and l=100um
is there any way to get a capacitor with less area??
i would like to give the input from outside the kit. i have the RS codeword, but to generate the 255 byte codeword in hardware and to pass one byte in one clockcycle to the FPGA is where i am facing the problem. also where can i check the output? the lcd or the led is not an option because the...
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