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I know this is really old thread but @nand_gates's code doesn't work good in my opinion. Follow the Best book about ADPLL I found that there is no error when signals J and K have opposite phase. Then result is square wave like J input. My simulation shows this unfortunatelly:
So I tried to...
Hi,
could someone explain me PM demodulation with 74LS297. I found in document "Digital Phase-Locked Loop Design Using SN54/74LS297" something like this:
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Reference 4 is "Digital phase processing for low-cost omega...
Hi,
Ive designed something and have very big problem. In ISE Synthesis finished without errors and warnings but when I viewed RTL Schematic there is one component not connected to others. I tried some combinations but nothing helps.
From this unconnected component, counter, I wanted use output...
Hi,
could somebody tell me what should be an input signal to ADPLL like 74HC297.
In LPLL it was almost sine wave as a telecommunication signal. Now I can receive this form ADC but thats are N length binary words. ADPLL has JK phase detector which needs bit after bit. What should I do with this?
Hi,
i need to design ADPLL in VHDL as PM demodulator. The best explained i found in Best, R. E. (2003), Phase-locked Loops: Design, Simulation and Applications, McGraw-Hill. It is something like 74HC297. Could you answer me these questions:
1. What kind of signal should be as an input if i...
About process i heard probably from someone at my university. It is really good to read that its diffrent. So what is the most important in RTL?
And what about compare two vectors? Should i search other way? I need to use that with counter, out signal is '1' when counter is above chosen value.
Hi,
i am newbie in VHDL and when i started with designing some questions come to mind:
1. I've found out that using signs '>' or '<' isn't a good practise. What is better way to compare two vectors, especially in 'if' ?
2. What i should avoid if i would like to write in RTL. I know that it...
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