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You should extract sdf and use this sdf in simulation. Of course your verilog cell library has only unit delays but during sdf annotation simulator replace these delays by delays from sdf file.
After synthesis you need some files to simulate netlist.
1. You need your netlist of course
2. You need sdf file
3. You need all verilog libraries which you use on design. Usually it is cell library, memory blocks.
In testbench you need to run command $sdf_annotate(). If you will not...
help:about lcd model
it is really better to check controller in FPGA first
especially if you want to use dithering for STN because in this case it is important not only waveform but algorithm of dithering too
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