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Hi,
i am simulating a low noise PGA in which i have observed the THD degradation at higher gain settings. Why?
normally we see the THD degradation for lower feedback resistance values(where gain is comparatively less) due to loading effects.
but got puzzled why at high gain settings?
Can...
hi jayanth,
from T/2 to T the current is flowing anti clock wise direction so the voltage accumulate as per B only. But when we are considering with respect to two nodes(as like vo), polarity was given like that.
clamper does not shift the phase, they shift the dc level.
at 0 to T/2 input is...
Re: Op Amp design for required specs
u can proceed folded cascode with CS as the second stage this will give you the required dc gain.
and it will meet the swing requirement also.
you can keep miller compensation or cascode compensation for the stability.
hi,
we have wide range of power amplifiers class A to classH as per my knowledge.
first can you what is the application of your project and power spec limit in your project?
based on that we can decide which topology will be optimum...
i hope you will come up with the above.
""If the load resistance is 10k ohms or more then the level is not attenuated and the distortion is much less.""
thanks GURU and FvM for your suggestions.
i had put a 10 K ohm load which improved the signal level and THD. but here i had put either M4 or M1 (see in the attachments) will be on...
hi All,
i have made a 8:1 mux (3 selection lines say three stages )using transmission gates as the switches.
i am getting the THD degraded, at every stage at the switch outputs.
i have observed the input signal is attenuated at the switch outputs.
I am not understand that why the...
hi, can anyone please explain how beta multiplier make a supply independent biasing.
i mean even for the +/-10% variations of vdd. how it provides a constant bias current?
thanks,
Bala....
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