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Recent content by baenisch

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    Custom Inductor design .13u Process

    Hi there, You might want to take a look into the Passive Component Designer from Cadence (available up to MMSIM7.11) and/or a EM-Solver like Sonnet. Both Tools require technology information: -sheet resistances -epsilons -layer thicknesses As far as I can remember PCD reads the data from the...
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    low drop out voltage regulator

    Your PSRR response does not really look like a PSRR response at all. Looks more like a loop gain curve ... Are you sure you followed erikl's instruction ? Add an AC value of 1V to your supply and run an AC simulation just as erikl proposed. Maybe one addition to that. AC is always small-signal...
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    low drop out voltage regulator

    Looks ok to me, beside maybe the the input pair could use some resizing for lower offset ;) It seems that your input pair is close to moderate/stron inversion which is ok for high bandwidth differential pairs. However you could place it in weak inversion for lowest offset. Is the cap at the...
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    low drop out voltage regulator

    And whats exactly the problem with the driver using more area then the amplifier ? Sometimes it simply comes out that way. Don't be shy, just do the layout. I know, it looks weird, but it's totally ok, as long as you meet your spec, also in an RC-extracted simulation. For such a big driver it...
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    How to realize a long delay on chip

    Interesting to hear. It seems that this topology is working much better if I compare your 12% to my 25% solution before trimming (even if I switch to 3sigma there is still a difference). I persume you trim the current to bring the delay on target right ? Best Regards (aus München ;) ) Andi
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    How to realize a long delay on chip

    Hi erikl I have a question about the accuracy of the circuit you proposed. How big is the spread of the delay if one considers a process spread of +- 4.5sigma, temperatur -40 to 140, supply variation ? I have used something similar in the past and the accuracy was not very good, up to +-25%...
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    How to realize a long delay on chip

    If you have a reliable clock available you can simply use a counter to count clockcycles. Apart from that you can use a slowed down inverterchain (loaded outputs or big length). This however yields in slopes that are totally messed up so you need to reconstruct proper slopes at the end of the...
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    Leakage Current Detector in 1T1C DRAM...Need Help

    I had a little time to think a little bit about a ASIC implemenation of a DRAM Maybe it's a good idea to store the information in differential form, meaning that you spend one extra bit to store the inverted info to a neighbouring cell. When reading the info you connect the cell and the inverted...
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    Why n+ and p+ are used by welltap?

    Directly connecting metal to a weakly doped n or p area usually ends in a schottky contact and not in an ohmic contact. Therefore a strongly doped contact area is formed to reduce this effect. Best Regards Andi
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    Sampling Theorem in MATLAB

    Why not use the 'stem' command ? Just use the vectors of x and t1 and type stem(t1,x) and you automatically get the plot of a time disrecte signal that still has continous values. Best Regards Andi
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    Leakage Current Detector in 1T1C DRAM...Need Help

    Hi Johnny Ok, thanks for the additional info. The fact that you'll build your storage array with MOS-Caps makes life a lot easier ;) Ok, first we sum up the leakage for a MOS-Cap that have an effect on cell retention here. The most important ones here will be sub-vt leakage of the select device...
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    Leakage Current Detector in 1T1C DRAM...Need Help

    Hi Johnny First of all, I'll try to answer your simpler questions ;) I have sent you a PM regarding some other stuff I need to know before going into more detail, as I have noticed that my first try to give you an answer got more and more complex ;))) In general you need a spec, wherever this...
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    on chip 7.5V voltage reference

    What about device reliability ? 7.5V for a 0.18um process looks a little bit to high ... or do you use a high voltage process with thicker oxids ??? Best Regards Andi
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    Leakage Current Detector in 1T1C DRAM...Need Help

    I forgot one important point which has been implemented in the latest DRAM designs. Shame on me. As most of the leakage mechanisms strongly depend on temperature a temperature dependand refresh is a good idea to dynamically change the refresh rate. This is spec for DDR3 but I remember that we...
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    Leakage Current Detector in 1T1C DRAM...Need Help

    Hi there In a real DRAM 1T1C design you will never have a leakage detection. You just set the refreshtime according to the minimum spec or, if your process is better, to a higher refresh time, as this saves a lot of power. If you want to implement a leakage detection you first need to collect...

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