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Sorry to reply late. I have done this. The thing is scan chain is always performed in sequential circuits. You dont have scan chains in a combinational logic so whenever you introduce a scan chain it changes the design to sequential.
you only need spf only if you have scan chains inserted in your design. if you don't have that in your design you can skip this step and generate the test patterns.
i know how LFSR based built in self test (BIST) works and how to detect faults but i am confused whether it will detect stuck at fault at a fanout point as the response analyzer compares two signature from the output of the circuit under test. we can identify the faults at primary inputs but how...
@blooz: i hv already gone through all these documents. i need something in depth.
thanks shivaram, the first link is quite convincing.
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@blooz: can you send the fourth link again. its not working. thank you
can anyone please send me the study material explaining the concept of linear feedback shift register(LFSR) and how it is applied for built in self test(BIST)
vcs is just a verilog simulator by synopsys. it is just like other simulators like modelsim or xilinx but the the difference is there is no interface in vcs. if you are getting an error saying unresolved modules that means something is wrong with the code. fix your code and it will work for you.
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