Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The error in in my layout part.
see, I only use an nmos in schematic and add some port to it. And just instance and nmos in my layout and add port by ctrl+p shortcut and label each metal and poly relatively to the port in schematic
ny drain and source are float how can they become short circuit...
Hey everyone
I have got a problem in layout lvs with assura.
when I try to lvs, I get an error that two nets are short circuited, while these nets are the drain and source of my transistor. How is it possible that drain and source short circuited?:(
Plz help me how to fix it:((.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
