Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by asping

  1. A

    What is Null Frequency?

    Hi everyone, Could anybody tell me what the Null frequency is in RF design? I can NOT find its explanation from google. Thanks.
  2. A

    Beginner in analog circuit design

    electronic principles by a.p. malvino. The critical I think is to test carefully the circuit you designed. From it you will find more and more...
  3. A

    Why do we calculate pole/zero location by hand ?

    pole/zero analysis? Suggest you to review the principle of signal processing
  4. A

    Formal verification and conventional verification

    Formal verification is to check if it is the same function between your RTL and netlist.
  5. A

    Information about SRAM and drawing layout for it

    SRAM you can write a script to create it automatically
  6. A

    power estimation by primepower

    maybe you can try the powermeter
  7. A

    how to Convert synthesized VHDL/Verilog to spice netlist

    vhdl to spice netlist converter v2lvs in calibre verilogIn in cadence and similar tool in Herculs of synopsys but I cannot remember the name
  8. A

    Help me understand hold time and hold time violation

    Understanding Hold time Hold time violation is the serious problem for a chip design. the clk time ended before the data ended , this is hold violation. If there are setup violation, the chip maybe be operate at low frequency, but hold violation,the chip will not work at any frequency.
  9. A

    how to get standard cell library in icfb

    icfb layout symbol you can define as below in the cds.lib file in the directory you start up the icfb. DEFINE <libname> <libpath/libname> example: DEFINE stdcell_lib /xxx/xxx/stdcell_lib
  10. A

    What kind of ADC should I choose?

    Is 6mw the total power of ADC and bandgap ?
  11. A

    How to estimate the soc chip power consumption?

    How to estimate the soc chip power consumption in order to decide how many power pad are needed before floorplan. Thanks!
  12. A

    Terminology for packages like QFP, BGA, Flip Chip

    I want to know some basic terminology and requirements about package such as QFP, BGA,Flip Chip,etc. Can anyone tell me some books or papers? Thanks.
See more

Part and Inventory Search

Back
Top