Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ashourism

  1. A

    MDAC PSS PSTB and PNoise

    hi I am simulating this MDAC using PSS , PSTB and PNoise i have the following Questions During PSS should i keep Input Frequency on or should i short it to Common Mode level? Also how to perform pnoise what is maximum side band? thanks
  2. A

    MDAC Circuit Issues for an 8 Bit Pipelined ADC

    Hi I am working on a Pipelined ADC 1. I have built an ideal system that gets an ENOB of 7.99 2. I created a Folded Cascode amplifier that settles in 3ns with GBW 200MHz and Gain 61dB and put it into the system then i got an ENOB of 7.8 but now i am trying to replace the DAC and the switches...
  3. A

    Two Stage amplifier Iss current Missmatch across SS corner

    Dear All I am trying to make a two stage OTA for a SC circuit for usage in a pipelined ADC it should possess a minimum GBW of 205 MHz across all corners however across the ss corner (UMC130rf) the current mirroring ratio get extremely missnmatced that it get multiplied by two from 65u Iss to...
  4. A

    Measuring Input or Output Capacitance of a buffer

    so i used Cadence calculator to get the imaginary part of (I/V) then averaged it to get the slope this will be the capacitance? What about the output i tried to the same technique but i got a non-linear curve
  5. A

    Measuring Input or Output Capacitance of a buffer

    Hi i am trying to measure the input and output capacitance of a buffer stage (for example) as i need to measure several other stages i set up the following circuit and i set the input voltage to 1.2 with AC Magnitude and Amplitude to 1.2 , also vdd is set to 1.2 then i calculated Zin =...
  6. A

    Switched Capacitor Circuits Transient Simulation on Cadence

    You know what W11 was the actual problem LOL :D man you are like a miracle that happened over the last two days in my life Thanks!
  7. A

    Switched Capacitor Circuits Transient Simulation on Cadence

    Really i can't find words to thank you, i am now trying to use my basic knowledge of switched cap to simulate this precision multiply by 2 and subtraction (MDAC) circuit used in pipelined ADC its based on the circuit shown here https://www.iadc.ca/Imran_Pipeline_ADC_tutorial_files/image003.gif...
  8. A

    Switched Capacitor Circuits Transient Simulation on Cadence

    I followed your suggestion and i got a significant change in output it follows however its not 2Vin its 1V during Phase2 and till phase1 comes again also there are some glitches that i can't interpret it Edit: i forgot to set C1 to 2 pF for Vout = 2Vin. however what about the glitches any...
  9. A

    Switched Capacitor Circuits Transient Simulation on Cadence

    First of all thanks for help, however I am not sure what can be wrong with this switch can you illustrate more? also I don't understand point four do you mean I shouldn't connect the switch to gnd and I should use a Vdc and set it to zero? Thanks
  10. A

    Switched Capacitor Circuits Transient Simulation on Cadence

    Hi, i am trying to simulate a basic ideal switched cap circuit to make a non inverting amplifier based on on analysis in Ch.12 of Razavi's : Design of Analog CMOS Integrated Circuits, ofc due to copyright i couldn't upload more than those two pictures but please if you have the book try to read...

Part and Inventory Search

Back
Top