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Recent content by ashik_na

  1. A

    ADPLL - How to design linear DCO ?

    hi, this is not about VCO. i am telling about DCO ( Digital Controlled oscillators )
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    ADPLL - How to design linear DCO ?

    Hi All, I am designing ADPLL for video applications. For this ADPLL, I am using DCO as oscillator. Delay cells are used to generate the oscillation. But frequency chara ( Freq Vs Code ) of the DCO is not linear. there is large Δfreq, change at high frequencies for small change in code by...
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    PLL architecture for Video analog front end

    PLL architecture for Video analog front end Hi all, I would like to design a PLL for video analog front end circuits (VAFE) for HDTV application. Could you please suggest , which type of PLL will be better for this application? And please explain with reasons. Thanks,
  4. A

    PLL architecture for Video analog front end

    Hi all, I would like to design a PLL for video analog front end circuits (VAFE) for HDTV application. Could you please suggest , which type of PLL will be better for this application? And please explain with reasons. Thanks,
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    Differential gain and phase measurement setup for Video DAC ( Current Steering)

    Yes. It is for video application. How can i measure Differential gain and phase measurement with Spice simulator at transitor level ?
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    Differential gain and phase measurement setup for Video DAC ( Current Steering)

    Thanks ... But now i am designing a 10 bit CMOS current steering DAC. So how can i apply the inputs and measure differential phase & gan ? How can i make a simulation set up for it ?
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    Differential gain and phase measurement setup for Video DAC ( Current Steering)

    Hi All, Good Day..!!! How can we measure the Differential gain error and phase error of a video DAC ( Current steering ) ? Please explain with simulation setup ... Thanking You,
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    input bandwidth of ADC used for HDTV application

    Thank you for ur reply... I am planning to implement this ADC for analog front end of HDTV display . Does 30MHz input frequency is required for this ADC to check its all dynamic characteristics ?
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    input bandwidth of ADC used for HDTV application

    dear all, what is the input bandwidth of ADC used for HDTV application ? Could you please attach the document related on that ? I am prefering time inerleaved SAR ADC for this HDTV application having 165Mhz clock freq.
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    Input driving stage for SAR ADC

    Dear all , I am designing a pipelined SAR ADC with having clock freq.>160MHz. i want to design an input driving circuit for this high speed ADC. [ I can't give more acquisition time to charge the CDAC caps. ] which is the most conveniet method to drive pipelined SAR ADC having clock frequency...
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    Architecture for 1.2V 50MHz GB op amp

    Re: 1.2V 50MHz GB Op amp Thank You for your consideration. My aim is , to design an op amp acting as a buffer to drive the CDAC capacitor of high speed sampling SAR ADC ( order of 200 Msps ). 1.we are using 65nm tehnology with 1.2V supply. 2. 3db bandwidth should be > 50MHz 3. Should have high...
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    Architecture for 1.2V 50MHz GB op amp

    Dear all, I want to design a low voltage op amp for interfacing with ADC ( at input stage ) .Supply is 1.2 V and it requires a 50MHz gain band with. ( almost flat upto 50MHz ). Any one please suggest me , which architecture can be used here ? please reply with circuit. Has PMOS diff. pair more...
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    how to dump waveform in vhdl

    Dump trn file Hi, How can i dump the unrequired signal from .trn file as in .fsdb file?
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    transistor optimization in hspice

    how can i optimize an opamp circuit using hspice ? i need help to optimize transistor more accurately using hspice..?
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    Current Steering DAC layout, placement and floor planning

    I am also needed this plz help us.....
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