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Recent content by Aser

  1. Aser

    trying to generate a random number in a particular range using lfsr

    You have not infere the LSFR generator. Let it generate 1023 data in its period. To put the data into the given range you can: - select from the data flow the output data which satisfy limitations, or -add 145 and scale the result by multiplication to (786-145)/1023, or - combine first two...
  2. Aser

    DAC sin wave Rom calculations LUT

    Here you are examples https://kanyevsky.kpi.ua/Studentam/labexercise%201.pdf. The outputted data is for the DAC input, which output voltage arrangement is out of the synthesable VHDL scope.
  3. Aser

    help: IIR Filter design

    Consider the lookahead computation. Due to the formula y(i)=ax(i)+by(i-1); by(i-1)=abx(i-1)+bby(i-2)=cx(i-1)+dy(i-2). The resulting equation is y(i)=ax(i)+cx(i-1)+dy(i-2). Here you are the feed forward path as in the FIR filter -it can be implemented in 300 MHz, and the feed back path with the...
  4. Aser

    help: IIR Filter design

    I mean so too. The idea is that by such a pipelining the algorithm remains the same. But the hardware volume decreases for the same throughput due to the implementation of parallel channels or stages in sequence. Sometimes due to the effective retiming the clock speed increases dramatically...
  5. Aser

    dsp and verilog in fpga implementation

    Uwe Meyer-Baese. Digital Signal Processing with Field Programmable Gate Arrays.Springer- 2007. DSP: Designing for Optimal Results. High-Performance DSP Using Virtex-4 FPGAs. Xilinx-2005
  6. Aser

    help: IIR Filter design

    If you double all the registers in the IIR filter then you can organize the pipelining. But you get two filter channels, and a single filter cycle increases in two clock cycles, and due to the pipelining the clock cycle can be decreased up to two times. Therefore, the IIR filter pipelining is...
  7. Aser

    Question,how read image in vhdl?

    All the information is present in the Xilinx site. The methods for preparing programs are present in proper application notes as well.
  8. Aser

    digital signal processing with FPGA

    DSP is usually the digital implementation of analog electronics tasks. In Power electronic you can measure precisely alternated currents to force the control of , say, electric motor by some algorithm. For such or similar task you need the computer power much less than 1 mln operations per...
  9. Aser

    Question,how read image in vhdl?

    The initial question was about pure VHDL. There is no idea to load and store the image in FPGA for the beginner. A simplest approach consists in using RS-232 interface. One can load 20 images sequentially from PC into block-RAM or outer SRAM,DRAM, and store it backward. For this purpose UART...
  10. Aser

    digital signal processing with FPGA

    Firstly, look at signal graphs, they both represent the DSP algorithm and can be equal to the DSP unit structure, i.e. addition, multiplication, delay nodes are mapped to adder, multiplier, register respectively. Secondly, Power electronics is rather slow to be controlled by FPGA, where the...
  11. Aser

    Question,how read image in vhdl?

    BMP is useful format for input and output iv VHDL. You can write the procedures to read and write such a file using the shared variables.
  12. Aser

    wanted code for distributed arithmetic fir filter

    You can generate proper VHDL code by the PDA IP core generator built in the Aldec AHDL simulator, which implements similar distributed arithmetic.
  13. Aser

    eigen value implementation in fpga

    Cordic is often used to rotate complex vectors, and very rarely is used to convert matrices. It was obviously useful when hardware multipliers were comparatively heavy. Now when the floating point cores are usual things it would be better to implement the usual algorithm to find eigen value of...
  14. Aser

    Not getting a locked signal

    Ive proven that the DCM behavioral model works improperly especially when the frequency must be increased. Therefore to debug a project I usually fix the clock frequency and substitute manually the DCM output by some additional clock generating process. Before synthesis I comment this process...
  15. Aser

    designing LUT using VHDL - please help

    Look at Active HDL, try in it TOOLS -> IP Core Generator -> PDA FIR core with any parameters, and it generates you a VHDL code with such a LUT coding.
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