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Recent content by arunbv123

  1. A

    enter a array with two input clock using verilog

    integer i,j; initial begin i=0; j=1; end always @ (clk1 or clk2) begin if (clk1) begin MEM_CH1[i]<=ADC1; i<=i+2; end else begin MEM_CH1[j]<=ADC2; j<=j+2; end end //but this only work if clk1 and clk2 are not...
  2. A

    [SOLVED] vhdl code to obtain 2^n for the input n can u help me plssssssss

    set y to all zeros(reset y to zero) and the make the Ith position high. y[7:0] <=00000000; //i is given by input; y[ i ]<=1;
  3. A

    Reset for Registers in FPGA?

    If you have so many modules to reset then use more than one reset pins ans short all of them.place them appropriately to get the reset in time
  4. A

    verilog question: instantiation Always block

    hi, Are u looking for the syntax to write an always block? or to a module instantiation?
  5. A

    FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17

    module find(clk,reset,V,a,p, ); parameter X=1; parameter NUM=5; parameter a1=2;//constants parameter a2=2; parameter b1=1; parameter b2=1; input clk,reset; inout [0:NUM-1]V; input [0:NUM-1]a; input [0:NUM-1]p; reg [0:NUM-1]ve;//temporary value reg ab1,ab2; assign V=vel;/*including...
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