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Recent content by arp

  1. A

    How if and case statements infer logic after synthesis?

    if vs case verilog If statement used for priority encoder where as case statement is used for Mux
  2. A

    what is "loop delay"?

    U can't ignore the delay of the gates... A simple example which gives solution to ur above diagram... Take a NOR gate and assume that one i/p is ground and other input is at high(say 1.5v) and so the output is at zero... Now u give a zero to the high i/p for a very short time and can u tell me...
  3. A

    INTEL INTERVIEW- urgent need help

    I feel u need to be gud in basics!! I attended the Intel interview after my bachelors !! they played around basic inverter (most of them r easy with small logic behind) n tested my programming skill from microprocessor to HDL's :) HR is cool ... u need to be gud at comm skills also ...as said by...
  4. A

    WinRAR Doubt...PLZ don't mind for posting in this sub-forum

    Rightclick on the file and click on the Add to Archive option then at bottom left there is a split option.. inthat give 5MB and do RAR.. It will generate 3 files of 5MB each :)
  5. A

    Guidelines for RTL and Behavioural

    See any book related to verilog, they mention some verilog behavioral programming like fork and join which are not used in RTL. Yes you can use + in the RTL For converting to gate level, the converter tools will use the best logic for ur code for example if u want to add a bit to the two bit...
  6. A

    Glitches in AND gate with two inputs

    glitch Since glitches may cause random o/p's, we use a flipflop at the o/p of a combi ckt. as Ankit said u need to make sure that the o/p of an combi ckt need to be settled before the clk edge to avoid any random behavior!! that means ur clk period depends on this!!
  7. A

    clock domain crossing and synchronizing

    Following document is very useful before you r looking for a synchron
  8. A

    Why signal should be stable in setup and hold window??

    Self study is the better way to understand this problem! Just draw a flipflop with gates and assume some delays for each gate and try solving this by changing inputs at different time intervals. Then you can easily understand why u require a stable signal in between setup n hold time !!
  9. A

    Help me design a counter with my conditions

    Counter design! U can use this logic----- use a reset signal to reset the counter initially.. if(reset) { cnt_en=0; cnt=0;} if (cnt==36) { cnt_en=0; cnt=0;} if (cnt_en) cnt=cnt+1; if (cnt==0 and en=1) cnt_en=1; this can be easily implemented in digital logic
  10. A

    how can I solve this problem

    if its a ready 1 bit signal then what the funzero said will be correct n u just need a buffer to do that...
  11. A

    Resistance measurement from SPEF file

    Hi utmseng Actually I am writing a script that which finds the values R and C for each net for the same block with different routes. I just want to get quick check on the percentage change of R&C's by changing the placement. I am just approximating the net resistance from the spef file. So in...
  12. A

    Resistance measurement from SPEF file

    Thanks Dynamicdude for the quick reply.. Actually I want to calculate the approximate R from the SPEF without going to the tools. for example this is the SPEF definiton of a net *D_NET *2069 166.454 *CONN *I *6022:SI I *C 13668.6 13352.2 *D SDFFRHQX1 *I *5720:B I *C 13667.7 12506.9 *D MX2X1...
  13. A

    Resistance measurement from SPEF file

    Hi, For calculating the NET RC component, in spef they are providing the lumped capacitance. Is there any methods for finding the approx. resistance of the node with out going to another tool!!! plz help me regarding this.. thanks arp
  14. A

    Questions about SPEF format

    Hi I had a small dbt in SPEF format. Can anybody please tell me the format in the given example: In the below example *D_NET *961 12.4793 *CONN *I *4372:B I *C 13637.8 12075.0 *D NAND2BX1 *I *4338:SI I *C 13642.4 12020.1 *D SDFFQX4 *I *4335:Q O *C 13641.4 12033.6 *D SDFFQX1 *I *4368:A1 I *C...
  15. A

    perl or tcl, which is better for eda scripting

    i m new to tcl and perl I want to learn perl is there any tips to learn it easily!!!
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