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The delay is only CK->Q, it's small.
I think there are no impact for the layout and timing. In the backend design.
####
/32
CLK -------> CLK32
If there are timing talk between CLK and CLK32, the backend engineer
would match the insertion delay for CLK&CLK32.
Re: what is difference of SRAM and Synchronous Rigster File
For big memory, i offen use sram. For small memory, i offen use regfile.
By the way, the access process is different between sram and regfile.
For cell based physical design, I think no related book. We could learn from EDA tools's
manual, there are so many concepts and experience in these manual. the best way it to
use tools to implement a example design.
StartRC can only extract real "physical nets",
NETS: netname,
When you flatten the hierarchical netlist to flat netlist, the netname must be found in the flat netlist.
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