Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by armardu

  1. A

    vmm_xactor.start_xactor() in vmm

    vmm start_xactor() hi , i'm so confused about vmm functions like start_xactor() and stop_xactor() in vmm_xactor class ,how they works ? please help me Added after 1 minutes: help !
  2. A

    How does a (9:2) compressor work ?

    hi guys i'm so confused when designing a 16*16 multiplier,i don't know exactly how (9:2) compressor works ,can anyone supply some good documations or explain it?. thanks
  3. A

    help ,carry skip adder

    can anyone offer some material about carry skip adder ,please! thankyou thankyou
  4. A

    verilog testbench book

    In ebooks forum, there are many books ,for example "Writing Testbench ".
  5. A

    Low-power design lessons and reference

    Low-power design Frequency Throttling is another interresting technique that can be used in combination with Voltage Scaling STA can become a nightmare when you mess around with all those parameters... but that is another story...
  6. A

    synopsys design compiler workshop

    primetime workshop lab Very good work!!... The stuff really is very helpful. But I am still looking for the document to follow this lab. Thank you very much!!
  7. A

    how to understand set_output_delay ?

    set_output_delay explain dear all i can't understand the pic below: set_output_delay 1.6 -clock clka -min out1 // min =min_path-hold?? set_output_delay 4.8 -clock clka -max out1 //max=max_path+setup?? plz help me and explain them in detail...
  8. A

    without wire load model

    Joined: 31 Oct 2007 Posts: 115 Helped: 7 Points: 303.90 Donate Down: 12.73MB Post19 Feb 2008 20:04 without wire load model Reply with quote Report this post to the moderators of this forum To do synthesis without WLM you need to create a WLM within your .lib with zero capacitance and zero...
  9. A

    Who has the SoC encounter Lab?

    umc18 training you can try this link for a tutorial on encounter. It helped me a lot. http://www.chiptalk.org/modules/wfsection/article.php?articleid=1 Thanks Abhishek
  10. A

    Advanced Synopsys DC workshop

    Synopsys DC a simple tutorial include in it's manual. hardly to find workshop manual.
  11. A

    How to verify a netlist generated by synthesis tool.

    gatelevel simulation the file u need: 1 netlist file 2 sdf file 3 synthesized memory block if u use cell library in you design
  12. A

    How to generate clock

    From digital view. all the generated clocks are from a standard external Oscillator or Crystal, chip RTL and synthesis only generated different frequency clocks for internal usage based on this standard clock. BTW, you can use other ways to generate clock without source.
  13. A

    Synopsys. 2007.03-SP*

    Of course the obvious ones such as un-connected outputs and multi-driven wires....... I personally think this is a rumor spread by Magma people.
  14. A

    Who has the SoC encounter Lab?

    cadence soc encounter gift https://www.cse.sc.edu/~jbakos/612/tutorials/encounter.shtml
  15. A

    reduce the ISE implementation time

    One disadvantage of inserting an extra flop is that you must now account for the extra clock cycle of latency in your system timing design. That's what pipelined design is all about, and sometimes it's not easy. If your long ISE run time occurs only during HDL compiling, then my area...
See more

Part and Inventory Search

Back
Top