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Recent content by arkoudinos

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    Integrating custom coprocessor with ZYNQ

    I've already studied some of the various interfaces I can use. However, I don't know how to implement them. For example, I came up with the following block design: however, I have many scratch-heads. As you can see I've already packaged my IP, but the only ports that are available are the AXI...
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    Integrating custom coprocessor with ZYNQ

    I have finally managed to make a custom IP for the Full-Search Motion Estimation Algorithm. Now that I've tested it and verified that it works, I want to move with the next step, interface it in some way with the ARM processor in the ZYNQ SoC. So I have some questions regarding both the...
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    Using process for two different tasks in VHDL

    OK, first of all, thank you very much for your answers. They helped me a lot in clarifying some misunderstandings (newbie here :P). Secondly, to be more precise, I'm trying to build a module that compares the value of a signal with a previous one. If the current value is smaller than the...
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    Using process for two different tasks in VHDL

    I am trying to test a simple compare circuit. I want this comparator to initialize its ouptut on reset, because it is needed by another part of the circuit. I've came up writing something like this: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use...
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    VHDL code optimization

    The generated signals are not being sent off chip, but are used as signals to other components of the design. You're also right about glitches. vGoodtimes, the design is relatively small and it will be used as a peripheral to an existing CPU. So designing another CPU will add extra complexity...
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    VHDL code optimization

    I have a particularly weird control unit to implement, which generates some control signals based only on the value of an internal counter, obviously counting clock cycles. Firstly I would like to ask how (un)common is to generate control signals based solely on the number of clock cycle...
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    FS Motion Estimation sample

    I'm trying to develop an optimized version for the FS motion estimation algorithm in hardware (FPGA design) in order to further develop an embedded system including it. However, it would be very helpful if I had a simple implementation (in VHDL preferrably) of this algorithm in order to study it...
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