Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by anushaas

  1. A

    Electro Dermal Activity signal analysis

    Hi, I have Electro Dermal Activity(EDA) signals obtained from 7 individuals during a mental arithmetic test. A typical EDA signal is shown below: Has anyone come across any specific sofwares exclusively used for EDA signal analysis?
  2. A

    Offset correction for a simple inverting amplifier

    I am sorry but I did not get you.The circuit has an inverting configuration.Then how is "offset amplified by the non-inverting gain of the amplifier "?
  3. A

    Offset correction for a simple inverting amplifier

    I am simulating a simple inverting amplifier configuration using LF444A IC in TINA. The circuit diagram is : The input VG1 is a square wave of 75Hz frequency and 22mV peak amplitude. Both R1 and R2 are 10k. Theoretically, output VF1 should be -VG1 but I am getting the positive peak of VF1 at...
  4. A

    How to analyse the uncertainty of nominal coefficients in a circuit design?

    Hi, My circuit has a Gain phase detector that generates two output voltages, VMAG and VPHS which is related to the magnitude ratio and phase difference of the input signals (VA1 and VA2 ) by the transfer function: The magnitude ratio, |Z| and phase difference, θ can be obtained from the...
  5. A

    Why is an unloaded buffer showing an offset ?

    I tried the circuit using OPA827 and INA163.The schematic is as shown below: The input waveform VG1 is obtained as: The output waveforms as obtained from two INA163 instrumentation amplifiers(VF1 and VF2 in schematic) are shown below: VF1: VF2: The waveform VF2 appers to have...
  6. A

    Why is an unloaded buffer showing an offset ?

    I tried using a new AD8041 opamp (as an unloaded buffer) and it also showed the same offset at it's output.However,a LF347(also as unloaded buffer) did not show any such offset. I shall try using some other opamp with 20MHz GBW as suggested by FvM
  7. A

    Why is an unloaded buffer showing an offset ?

    [Moved]How to remove DC offset from signal? I am implementing the following schematic on a NI ELVIS II+ board The wave form at point A in the schematic is shown below: Initially,without a POT in the feedback path of OP1,the waveform at point B showed an offset as can be seen below...
  8. A

    Why is an unloaded buffer showing an offset ?

    Thank you Sir.That helped.I put a pot in series to negative input,adjusted it till the offset is removed
  9. A

    Why is an unloaded buffer showing an offset ?

    Here is the schematic: The waveforms shown above are VG1(without offset) and VF1(with offset)
  10. A

    Why is an unloaded buffer showing an offset ?

    This is the waveform at the input of buffer: The output of unloaded buffer is as below:
  11. A

    Why is an unloaded buffer showing an offset ?

    I am using an AD8041 IC as a buffer for a 0.2Vpp sinewave input at 1kHz from the function generator.The circuit is set on an NI Elvis II+ board.The buffer is unloaded but there occurs some offset at the output of the buffer. Why is this happening?
  12. A

    Gain and phase measurement using AD8302

    Hi, I am using an AD8302 IC for gain and phase measurement of two signal inputs within a frequency range of 1Hz to 1MHz. It is mentioned in the Application Note AN-691 that the IC need to be used in the following configuration to enable its use in low frequency applications. I used a +5V...
  13. A

    Simulation and Hardware mismatch

    I did consider that.The probes used for measurement were properly compensated.I don't know what else to do.I suppose that the breadboard capacitance would be 2pF approx. and that definitely will not cause a 25pF parallel to load. The NI Elvis scope channel has an input impedance of 1MOhm with...
  14. A

    Simulation and Hardware mismatch

    Here it is. The circuit is as shown below.VF1 is now the output of first amplifier stage The frequency response on simulation is: Response from hardware implementation:
  15. A

    Simulation and Hardware mismatch

    R6 is not wirewound.It is a carbon film resistor of 10k. I tried the above circuit with a 10pF across R3 (6.8pF across R2 was removed).The frequency response obtained during simulation and hardware implementation is as shown below: Simulation: **broken link removed** Response for Hardware...

Part and Inventory Search

Back
Top