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Recent content by anmolvlsi13

  1. A

    about how to access DDR SDRAM

    Look address is different to data bits. it can be 32,64,128......... any thing there are so many thing in ddr(mode register e.g) Go to xilinx & refer application note for ddr .......... Anmol
  2. A

    critical path in SRAM

    hi nitu, wat i said before is the universal concept,. The critical path in an SRAM is the Read Operation. The bit line has to be discharged thro 2 transistors in series. Devices have to be sized to prevent the intermediate node from charging up too much. For the write operation, all constraints...
  3. A

    help me with a synthesis concept

    As in desigining of FSM we shold not mix the Seq. and Combinational logic ,otherwise unwanted Latch would be inferred. Anmol
  4. A

    What is ASIC and how does it differ from FPGA?

    What is ASIC ? ASIC ------It is full custom means we are starting from scratch. FPGA.......It is part of Asic (SEMI CUSTOM). Before we go for ASIC first we tested on FPGA. ANMOL
  5. A

    Need fundamentals of SDRAM controller

    Hi go FIRST TO XILINX .COM AND LOOK FOR APPLICATION NOTE ONE IS APP 702 FRM THERE U CAN GET THE SPECIFIC MICRON SHEET . aLSO LOOK FOR JEDEC SPECIFICATION ANMOL
  6. A

    about how to access DDR SDRAM

    DDR sDRAM access not depends on bits. IT IS THE BANK(Row & Coloumn) through which you can access the data.Again i am confused wat you are saying 30 & 28 bits... wat is this data or address bits. Any how It is the mode reg. that consists of data+address..... if you don't want some bits you can...
  7. A

    what is the feature size, gate length or gate pitch?

    gate-pitch and half-pitch feature size is nothing but the Gate length. Anmol
  8. A

    what is the difference between "port" and "pi

    Port refers to in,out and inout....... i.e wire & reg. internal pin for different modules. As a pin where we can apply the input & get the output in TOPLevel MODULE. Anmol
  9. A

    NAND or NOR is faster

    Nand is Faster whatever Technology USE? Because Pmos w/l is 3 times than NMOS. So, risetime is directly prop. to AREA i.e W Since Wp =3 Wn. SO, Trp =3 Trn Anmol
  10. A

    help me with a synthesis concept : Latch (2)

    FF is edge sensitive ,glitch problem is less occur . LATCH is Level Sensitive, so if at the input any glitches is there for constat period it will be propogated to output. Anmol
  11. A

    Suggest me some references about timing issues

    timing issues Refer book Wakerly Anmol
  12. A

    Which FSM is better for designing in Verilog?

    melay and moore machine examples Mealy is Transition based Moore is Stae based. Anmol
  13. A

    Clock domain crossing timing error

    synchronization false path timing Use more FF instead of 2 to synchronize the clk as increases the FFreduce the Probability of Metastabilty. Anmol
  14. A

    Definition of setup and hold time

    setup and hold time Set up time iprovide the MAX. Freq. of the ckt Hold time describe the functioning of Ckt. It occurs because of Metastabilty problems. Anmol
  15. A

    critical path in SRAM

    Definately size of PMOS is 3 times larger than NMOS. So mobilty is 1/3 of NMOS. iIn General Crital Path is largest distance frm I/P to O/P, Reg to O/P,Reg to Reg.,I/p to Reg.You need to reduce the Critical Path by including FF. Anmol
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