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delay model veriloga
I found the solution:
One can use the Verilog-A "delay()" function or the Verilog-AMS "absdelay()" function with the maxdelay parameter passed properly and letting the delay value be varying.
veriloga delay
Hi all,
Can anyone kindly provide me with a Verilog-A/AMS model of a voltage-controlled delay line?
I know this is a DISTRIBUTED component, but there might be a good lumped-model approximation for it.
Thanks,
Ahmed
circuit read-in.
To include a model library, in the Analog Design Environment, select Setup >> Model Libraries and select the *.scs file containing the device models.
hotfix for ic5141
I found out that (as other posts have already confirmed), starting the installation from the update (ISR) CDs is the right thing to do. Don't start installation from the base CDs. They will not recognize the update CDs.
cadence ic5141 libc
An important thing to note is that:
Before the last step of the installation procedure (which is "Configuting Installed Products"), you should see if the "tools" symbolic link (which points to IC5141/tools.lnx86) has been created or not. If not, you should create it before...
1- Copy the following files to /tmp/IUS56_Install;
Base_IUS56_lnx86_1of3.tar
Base_IUS56_lnx86_2of3.tar
Base_IUS56_lnx86_3of3.tar
2- Extract these files.They all contribute the following directories to the IUS56_lnx86.Base directory:
CDROM1
CDROM2
CDROM3
3- Open a shell and...
ius 5.6
I found the soution. You must enter this shell command before starting SETUP.SH script of any Cadence software;
export _POSIX2_VERSION='199209'
It seems this sets the compliance of the shell with the older version of POSIX specification so that you don't need an older Centos.
Thanks
centos-5.3 ic5141
Indeed, a friend of mine had IUS5.6 installed on Centos4. But I have to get it installed on > Centos5 to link it with IC5141 (for Verilog-AMS simulations).
Many thanks for pointing me to the given topic. I will try the suggested solution.
cadence on centos 5.3
While I was installing Cadence Incisive Unified Simulator (IUS) 5.6, I got this message:
"
Checking data files...
Executing control programs (pre-load) ...
sort: open failed: +3: No such file or directory
expr: syntax error
"
I was installing on Linux Centos 5.3.
I...
Re: SVA
Some subset of assertion languages (SVA/PSL) can be synthesized. Actually, assertion-based verification had been done using finite-state machines before SVA/PSL/Sugar were invented. Modern-day tools (like Cadence Incisive) can synthesize assertions and verify them on...
how to install cadence ic5141
This topic is about installing Cadence IC5141 on Centos5 distribution of Linux.
This post augments the topic at the following link:
This installation was implemented on a Sony VAIO laptop. Installation of IC5141 failed on Fedora Core 9 run by this hardware. As...
convert spice to ibis
Using Cadence's Allegro Model Integrity you can make IBIS models from Spice models.
Model Integrity supports an HSPICE-to-IBIS conversion module that assists in creating IBIS models from HSPICE simulation runs. Use the output of the HSPICE simulation run, IBIS, and buffer...
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