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Recent content by anantha_09

  1. A

    How to find number of registers in a design?

    synopsys DC can report num of regs in design
  2. A

    Lec.... Ignore inputs

    You cannot ignore input pins, unlike output pins. you need to tie them to zero.
  3. A

    What are the types of caches?

    Re: Type of caches Hi Can you post more info on this please Thanks Anantha
  4. A

    Can anyone clear my synthsis doubt?

    DC uses wire load models to estimate RC delay before layout. These wire load models are created by ASIC vendor and are extracted from the technology library. If no wire load model is specified DC selects automatically. Firstly use "auto_wire_load_selection = false" command to disable...
  5. A

    synchronous clock domain crossing

    **broken link removed** https://www.asic-world.com/tidbits/clock_domain.html
  6. A

    What is the effect of clock gating in design?

    Re: Clock Gating >>>>>It can lead to glitches even though it is used a low power t/q and it can be done in several ways like using an and gate.***But, a latch implementation is widely used to avoid glitches ***** latches are prone to glitches coz of enable being high. F/F avoid glitches...
  7. A

    The diffences between unsigned.all, numeric.all and arith.all (VHDL)

    can any one let me know the diffences between unsigned.all, numeric.all and arith.all? when to use which package? and what would be the implications Thanks Anantha
  8. A

    Job opportunity in US for Physical design Engineers???

    as far as i know the most common choice for indians to work in us would be h1b
  9. A

    How to convert the gds file to .v or .spice netlist ?

    Re: regarding the gds I dont think it is possible reverse engineering is not possible i.e u cannot know the verilog or may be design if u have GDS and also if you hav net list Added after 8 seconds: I dont think it is possible reverse engineering is not possible i.e u cannot know the...
  10. A

    Job opportunity in US for Physical design Engineers???

    I dont think there are consulatncies which are related to VLSI design unlike there are many consulatncies which work on SW domain. There are plenty of jobs in US for VLSI design engineers, but the candidate must be eligible to live and work in US
  11. A

    How to increase logic space in palladium emulator?

    Re: palladium emulator wat do u mean break the logic?
  12. A

    How to increase logic space in palladium emulator?

    any one here working with cadence palladium emulator? I am trying to build an IP and it needs more logic space how do i increase logic resource ?
  13. A

    Looking for tutorials on conformal

    lec tutorial conformal hi iam new starter for LEC and i am using conformal. i am managed to find some useful stuff abt LEC on the net. can anyone please post some tutorials on conformal which would be of great help. thanks anantha
  14. A

    How to produce this sequence using shift register?

    Re: interview question hav u got any more problems of this kind or let me know wher can i find some of these kind
  15. A

    How many bits are there in the result of an 8x8 multiply operation?

    How many bits are there in the result of an 8x8 multiply operation? How many 4x4 multipliers would you need to split a single 8x8 multiply into multiple 4x4 multipliers?
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