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Recent content by anant

  1. A

    DWRR & LINK-LIST Verification

    what is the best way to verify DWRR & LINK LIST RTL Design.? thanks
  2. A

    OVM / VMM Performance.

    ovm vmm Does anybody know which methodology is better as per as performance is concern.? Assuming that you are implementing a same testbench in vmm & ovm. thanks
  3. A

    What are the salaries in Asia?

    Re: Salaries in ASIA Does anybody know what is the salary in INDIA for asic verification /design engineers with 8 -10 yrs experience.
  4. A

    Need to download SystemVerilog Plugins

    eclipse sv plugins does anyone know from where to download SystemVerilog Plugins. Any experience with that ..is there any other ide better than this. thanks
  5. A

    Help needed - solution for error in nc-verilog

    Re: NC-Verliog Error check setting for variable WORKDISK_LOC. Make sure that you are setting is correctly.
  6. A

    Requirements for fresher VLSI job in Pune , India

    netxen system pvt are there any product companies? most of them are service.
  7. A

    Transition time violations

    max transition time what is transition time violations?How is it different from setup & hold violation?
  8. A

    $random & $urandon - systemVerilong

    How to pass seed information to $random & $urandom so that test scenario can be reproduced.
  9. A

    Structuring C++ code -- OOP

    structuring c++ code Can anyone suggest good book on C++ which will have following any information. - OOP concepts - apply OOP any programming - how to structure your code --based on interfcaces - application implementation standard practices.
  10. A

    Which country has best opportunities (work and Pay) in VLSI

    Re: Which country has best opportunities (work and Pay) in V I too heard that working hours are more in Japan. More work to less work Japan - India - US - Europe. salaries high to low US - Europe - Japan - India
  11. A

    Interview question about a FIFO depth

    interview question fifo depth I dont know if this is the right section for these types of questions. anyways my answer is 25 .
  12. A

    Possible ways of Designing Latch from Mux and Flip - Flop

    Re: Possible ways of Designing Latch from Mux and Flip - Flo if you have a mux with input A & B, select signal = sel, output = y. A gets selected when sel = 1. connect y to B, this will make it a latch
  13. A

    VERIFICATION METHODOLOGY

    method 2 is better. if it simulates back to back packet/frames. other way is restrict the packet generation to small number say 50. This way packets will always be available to driver also will not consume much memory.
  14. A

    Difference between latch and transparent latch

    latches are designed to be transparent. by adding enable control signal to latch it can be made non-transparent which mean when enable is active output follows input. latch does not have a clock signal.
  15. A

    Verification: SystemVerilog vs. Specman (e) - who's on top?

    systemverilog aop both sc, e and sv all are good..depends on what type of design is being verified.
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