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Recent content by analog_ambi

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    On chip balun single ended to differential

    Thanks BigBoss!!
  2. A

    On chip balun single ended to differential

    But the sig gen will have 50 ohm resistance right? Is it not required to match?
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    LVS errror :BAd componenet sub type

    Hi, When i use component havar in cmrf8sf ibm130 technology then i get an error called bad component sub type D(havar) DDo(net1) When i checked the .src.net and .sp file then the instances have different order of parameters. How do i fix it?
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    On chip balun single ended to differential

    On chip balun for single ended to diff Today at 12:14pm Quote Modify Hi, I am using a balun to convert single ended signal (from signal generator) to differential (onchip). 1. Is it necessary to ground the center tap of secondary? I am AC coupling the differential. 2. Since sig gen has 50 ohm...
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    Choosing self resonant frequncy of offchip inductor

    Hi, I need an offchip inductor L= 10nH for matching LNA input @ 2.4Ghz. How do I choose the self resonant frequency? 2X 3x 4X?
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    Injection locked oscillator: direct v/s indirect

    Hi, Which method of injection is low power consuming in injection locked oscillator? 1. Direct injection where MOS is connected in parallel to the tank 2. Indirect injection where MOS is connected like a diff pair
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    choosing inductor for low power consumption of vco

    Hi, I have two inductors: L1=2nH Q1=15 Rp1 (Parallel)=450 ohm L2=4nH Q=11 Rp2(Parallel)=500 ohm where Q=Rp/Lw If I use them in VCO I want to know which one will provide low power consumption. I think Rp2 is greater and hence less -gm will be required to start up and hence inductor 2 will be...
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    PA design: issue with parasitic capacitance (bondpad+bondwire+pack pad+pcb)

    Hi, I am designing a PA as shown in schematic. Some specs are: 2.4 GHz ultra low power (<1mA) moderate linearity (modulation is QPSK, moderate PAR, either class A or class AB) The problem is my gain falls by 2dB (w.r.t mid band gain) at 2.4GHz when O/P is loaded with 200f parasitic...
  9. A

    generate bias voltage of power amplifier

    goldsmith: I am designing a cmos IC transmitter. By gali-5 do u mean discrete component? Mine is a IC design issue. Are u sure class E , F and C can handle linearity requirement of QPSK modulation? The peak to average ratio for my case is 4dB.
  10. A

    generate bias voltage of power amplifier

    This circuit will be power amplifier for ultra low power RF transmitter with EIRP=-5dBm and freq=2.4GHz. The first stage shall be class AB but the last stage is class A (cant help due to linearity requirement of modulation). Everything is integrated CMOS. The methods suggested by u will...
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    generate bias voltage of power amplifier

    What is the best way to generate bias voltage VB1, VB2 and VB3?
  12. A

    Transient response of the vco control voltage of a PLL

    Hi, 1. I have attached transient response of the control voltage of my PLL in Cadence. This is NOT behavioral reponse. 2. From t=0 to 100us it is the startup time. No frequency step provided 3. At t=170us a frequency step of 40MHz (max size for the pll) is provided and resulting transient...
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    op amp used in charge pumps for charge sharing / mismatch

    Hi, In charge pumps to remove charge sharing a unity gain opamp is used. Again to minise current mismatch or increase resistance of current sources, a servo opamp can be used as shown in razavi books. I want to know which method is more helpful in minimising spurs? I have power constaraint and...
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    vco control voltage in pll behavioral simulation in simulink

    I checked Phase margin and I get similar response even with 75 degree PM
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    vco control voltage in pll behavioral simulation in simulink

    Hi, i simulated my pll using simulink n time domain and ended up with peculiar control voltage even with 60 deg/75deg PM. Fig 1 shows the output of loop filter. Fig. 2 shows output after VDD saturation. I want my vco control voltage to slightly rise from 0 at t=0 and settle as if critically...
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