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Recent content by Amruth

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    [SOLVED] what is clock latency and clock uncertainty

    clock source latency Hey MarcS thanx ... great explanation
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    DRC/LVS in SOC-Encounter - running drc in encounter

    Re: DRC/LVS in SOC-Encounter yes i agree with them .... calibre is signoff tool for verification .. because the names of the nets in the pnr tool not pushed down from the top level but when we do gdsii it willpush down net name 4m top hierarachy ... to botom ( This is in LVS point of view)...
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    Need help regarding booth Algorithm

    HI , Please help to understand the Booth's Multiplication/Divison algorithm. its good enough for me if any one can send the notes.. Thanks in advance
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    Could sb help me out regarding Booth Multiplier Algorithm?

    Regarding BOOTH Algorith HI . Could any one help me out regarding Booth Multiplier Algorithm...
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    what is .lib,LEF,SDC,NETLIST.V,?Plz tell me in detail and wi

    Re: what is .lib,LEF,SDC,NETLIST.V,?Plz tell me in detail an LEF = library extraction format it also contains RC values also SDC contains clock information,false path and multi cycle path, cap,fanout and transition values .v is gate level net list file which is o/p from synthesis .lib also...
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    What is the best synthesis tool available on the market ?

    Re: Synthesis Tool Synopsys Design Compiler
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    synchronization from fast to slow domain

    in that case we use clock syncronization
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    Design of deskew block

    hi is that related to negative skew ...???
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    Multi Vt and Multi Voltage

    leakage power multi-threshold vt hi, multi VT cells are cells that has multi threshold voltage but same operating voltage.for multi voltage cells the operating voltage is different. these cells comes in to picture when powerislands comes into design. i hope it will help you
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    Voltage and cell delay of a cell (STA)

    hi, for standard cell design the process is same but we have different voltage and temp i.e,min and max. but u r design has to work in all circumstances so u need to verify u r cell timing in different variations. so delay is impacted by all variables we cant say the percentage of contribution.
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    Why the size of inverters in buffer design gradually increases?

    Re: Buffer design that cocept is called as Gate sizing. if we place one large cell it consumes high power. and u ll get tansition violations..etc
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    DFT query about netlist that has flops with clock enable pin

    Re: DFT query we cant conform with that our design has gated clock. every flop has clock enable pin . gated clock is use to enable particular logic ( group of flip flops)
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    Static Timing analysys

    hi its available in SoC user guide and Astro user guide .
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    How to save and load Virtuoso Bindkeys settings?

    setting bindkeys in virtuoso for bindkeys there is one script file , if u want create u r keys edit that file and save it reflects every time no need to upload every time when u r invoking in to the virtuso. that is script file. i hope it will help u
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    What is the difference between a hierarchical design and flat design?

    Re: Physical design... hi the above answer is correct
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