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Recent content by ammar_kurd

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    Magic layout software grid is not showing.

    Thanks Srizbf, I have already tried that but it didn't work.
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    Magic layout software grid is not showing.

    Thanks Klaus, after changing the screen resolution from 1366x768 to any other resolution I can see the grid but the screen viewing is really bad, when I revert back to 1366x768 the grid does not disappear and all is good, I am not sure if it is a bug or not though, but now I have this situation...
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    Magic layout software grid is not showing.

    Hello all, I am working on my laptop and I need help with Magic layout software, I need to get the grid to appear, even though I used the command "grid on" and pressed "g" on the keyboard I can't see the grid. Do I need to set some settings for the display screen or something? Thanks in advance.
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    Need a suggestion for SoC Communication References

    I am not aware of the terminology of inter and intra, but, basically what I am looking for is say in the same chip you have two cores how would they communicate, what protocols and architecture is used commonly. Sorry for not using the proper terminology.
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    Need a suggestion for SoC Communication References

    Hello, I am looking for good references on the topic of the of chip communication for SoC from an architecture and protocols point of view not circuit level, any suggestion for books or tutorials is appreciatively welcomed. Thanks in advance.
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    [SOLVED] Question about a multiplexer based bus.

    Re: Question about a mltuiplexer based bus. Yes I have made a TOP module and tested the design again, it was an IO problem. I was trying to implement something as shown in the picture from Morries Mano book but only with a 32 bit register file of 32 registers. Anyway I figured that I don't need...
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    [SOLVED] Question about a multiplexer based bus.

    Question about a mltuiplexer based bus. Hello all, If I want to make a bus for 32 registers in a register file each of 32 bits, if this bus is implemented as a multiplexer based bus is it going to be as seen in the picture? that is first, second how to implement in Verilog in a way that will...
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    [SOLVED] Verilog: what is inferred when synthesising a reg type?

    What is the difference between a reg type in Verilog and an actual register? When using a reg type what will be inferred by synthesis tools, is it a flip-flop? if it was what type of flip-flop? I am a little bit confused since a register (reg) is basically a flip-flop but here I read it can...
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    [SOLVED] Verilog: What is the proper way to synthesis a JK flip flop with reset?

    I am trying to write a synthesisable Verilog module for a JK with a reset, I have tried this module JK_FF( input J, input K, input reset, input CLK, output reg Q ); always @(posedge CLK) begin if (reset == 1'b0) begin Q <= 1'b0; end case({J,K})...
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    is it worth it to learn Chisel HDL

    Hello everyone, What do you think of Chisel HDL made possible by UC Berkeley? is it worth spending time learning it? is there any major benefit in contrast to Verilog or VHDL? Thanks in advance.
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    [SOLVED] Qustion: Hold-time and propagation-delay.

    It is true what you said about hold-time, but how this is related to propagation delay, and are you sure it is a mistake? I will look for the errata and get back to you.
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    [SOLVED] Qustion: Hold-time and propagation-delay.

    Hello everyone, In the book "Logic and Computer Design Fundamentals by M.Morris Mano and Charles R.Kime", after defining what a hold-time is and what a propagation-delay is, it is said that "Since Changes of the outputs are separated from the control by the inputs, the minimum propagation-delay...
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    Advice regarding a RISC course or a book

    @bhaskarskj1 I really don't have a specifications I just want to learn processor design hands-on. by the way what do you mean by "specifications", do you mean a specific ISA?
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    Advice regarding a RISC course or a book

    Hello all, What is in your opinion a good book or a free online course that revolves around designing a processor with RISC ISA?. MIPS for example or any other processor, but it has to be hands-on like implementation on FPGA preferably using Verilog. thanks in advance.
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    Designing Edge Detector Verilog Logic

    sorry about the confusion the diagram is the correct description, I switched between signal1 and signal2 in the description. - - - Updated - - - Can you please elaborate more regarding this option?
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