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Recent content by amitk3553

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    encryption of link and data

    There are two terms we use in encryption 1) Enrypting a link between devices 2) encryption of data to be transmitted in between devices I had seen these terms in bluetooth host and controller. So are they one or same thing or both terms are having different meanings?
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    Program blocks in System Verilog

    What is the meaning of following "module (design) can not call task/function inside a program block. But a program can call task/function inside module (design)" Please explain it!! Thanks
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    role of gasp mode, sel_rom, mo_force_wd in watchdog

    hello, Please let me know the role of followings in watchdog timer 1) mo_force_wd 2) sel_rom 3) gasp mode Regards cam
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    Clarification in CCM (authentication and encryption)

    Hello, Could somebody explain me followings in CCM mode 1) Meaning of M(size of authentication) and L(Size of length field)? 2) What is nonce and purpose of nonce? 3) Nonce of 15-L octets. what is meaning of 15-L octets? Regards cam
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    systemC fifo vs C++ queues(linked list)

    I have to develop memory locations like fifo or something to store in SystemC: we have by default sc_fifo in systemC We create queues(linked list) using pointer in c++.So which approach would be most useful? sc_fifo or queues as in C++.as we can perform same operation through both approaches and...
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    How we decide the polynomial for CRC

    thanks I am working on hardware implementation
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    How we decide the polynomial for CRC

    could you brief this with some example of application? Is this some related to increasing precision or accuracy by increasing degree of polynomial? and one more thing output/input is serial so output value is bit by bit and output depends on input like if we apply 8 bit input serially then at...
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    How we decide the polynomial for CRC

    On what basis we decide the polynomial equation. Is there criteria for that? must be there? Thanks with Regards cam
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    How to avoid unwanted logic removal during synthesis?

    Re: How to avoid unwanted logic removal during synthesis I think you should carefully define the clock constraint, its the only single way to tell design compiler something u want to tell.
  10. A

    F-QPSK modulation technique

    Hello guys, Please brief the F-QPSK technique. Regards cam
  11. A

    Area constraint in synthesis

    Hello all, We use constraint like set maximum area or set minimum area in synthesis constraints Then about which area we talk??? Its area of an IP or area of cell or area of something else? Regards cam
  12. A

    Design aspects of Latch based Design

    What would be the differences in Latch based and FF based designs in terms of timing, area and synthesis? Thanks cam
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    Is it possible to do a complete latch based digital design for an ASIC ??

    Re: Latch based design for ASIC There are some problems in DFT and STA of Latch based design. Could somebody tell me about these problems? Thanks With Regards cam
  14. A

    Ping pong effect in RTL compilation

    we need to register all Outputs(Means output should come from registers) to prevent ping-pong effects!!!!!!!!! So want to know exactly what is ping ponging in RTL which we have to prevent form ping ponging to achieve good synthesis results. I think I cannot understand this concept by just...
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    Ping pong effect in RTL compilation

    Hello all, Please tell me what does mean by ping pong in RTL compilation. THanks!!!!!!!!!!!!!! Regards cam
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