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Recent content by amitgangwar_vlsi

  1. A

    Inferring Vs Instantiation ??

    inferring is the logic which tool generate automatically which you dont describe.... instantiation is the logic which tool generate which you describe....
  2. A

    Please clear my doubts

    in VHDL you can write a procedure in a package for adder and then you can call it as concurrent or sequential statement whatever you want in multiplier..... i did not under stand that how are you designing adder using for loop...
  3. A

    "wait for" statement inside process with a sensiti

    Re: "wait for" statement inside process with a sen try AFTER statement.......... i m not sure but try this....
  4. A

    "wait for" statement inside process with a sensiti

    Re: "wait for" statement inside process with a sen you can use either sensitivity list or wait statement within a process only....
  5. A

    Doubt again.................

    what is the length of numbers????
  6. A

    Usage of bit file of an FIR filter

    Re: bit file usage that input out put you can get from the simulink model designed.... you can give same input to the FPGA also. if you are using any prebuilt model then there will be some doc for that and if you designed yourself then you should know that... anyways...system generator also...
  7. A

    Problem with system generator

    matlab version unsupported system generator 10.1 i dont know abt 9.2..... i facecd same problem. xilinx 9.2 dose not support matlab 7.1. xilinx 7.1 support only matlab 7.1. matlab 7.1 support only xilinx 7.1. amit
  8. A

    Two's complement using minimum hardware

    very good logic... i appreciate that.... but i want to minimize some gate in that logic further... we can remove the 1st OR and XOR gate because when we take the 2's complement then LSB always same. so there is no need of 1st xor and. we are transfering the GND to the first or gate and its...
  9. A

    Two's complement using minimum hardware

    if u do not use serial conersion... then You have to use atleast n bit adder and n xor gates... i could not understand ur logic...
  10. A

    How to distinguish between two different SLAVE devices?

    Re: IIC Slave Question each device must be of different addresses... so there will be no problem to detect the slave device....
  11. A

    Help me with the code_ parallel to serial converter...

    your parallel to serial code is not right... u did not use PAR input... i think u r getting output 0 ... m i right...first chek ur design code.....
  12. A

    Problem with system generator

    problem with path in system generator matlab should also be of same version 10.1
  13. A

    Problem with system generator

    ise 10.1 system generator matlab version both should be of same version... MATLAB, System Generator and XILINX
  14. A

    combinatorial logic coding style question

    if you do not write clk1 and clk2 in sensitivity list.. then hardware generated will be right and synthesis will be right. but in simulation you will get the wrong out put. and your synthesis and simulation result will be differ. there are some constructs which are ignored by the synthesis tool.
  15. A

    display the output on LCD on SPARTAN 3E KIT

    mostrar un mensaje en la lcd de la spartan 3e it will depend upon the controller used within the LCD... read kit user guide... and according to the controller timing generate the output which you will give to the lcd.. your controller data line would be 4 0r 8 ... read out the kit user guide...
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