Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by amin_8460

  1. A

    spartan6 vs virtex6 speed difference

    Hi Is is being said that virtex6 is faster than spartan6, why? does the speed depend upon manufacturing process? thanks Amin
  2. A

    Xilinx FPGA timing Constraint

    The delay error is between two Flip Flop and so the pipeline method could not use in this situation. My problem is routing not synthesize.
  3. A

    Xilinx FPGA timing Constraint

    Hi there I am using a SPARTAN6 speed grade 3 and there is a high speed SDR SRAM In my board. I've used PLL to generate clock and out to SRAM. I set timing constraint but the max frequency I achieved is 125 MHz. If I increase the output clock of PLL to 150 MHz I have timing constraint error...
  4. A

    Latch-up performance in cmos logic

    hi there What does it mean when the datasheet says: "Latch-up performance exceeds 100 mA" 100 mA in where? IO or VCC? I already read the JEDEC standard but I could not clarify it for myself.
  5. A

    FPGA Banks Charactristics

    Hi I read this documents already. I think I couldn't clear my question. Thanks
  6. A

    FPGA Banks Charactristics

    Hi I'm using Spartan6 but I could not find relative document to answer exactly my question.
  7. A

    FPGA Banks Charactristics

    Hi there First, I state my problem: I need to connect a high speed SRAM to a Xilinx FPGA. May I use different banks of FPGA for the signals of SRAM or I must use one bank.( I will make same length for both situation) my question is: Is there any timing characteristic difference between banks...
See more

Part and Inventory Search

Back
Top