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Recent content by AMCC

  1. A

    why do we need lay out based on VHDL

    If you have access to tools like IODesigner (from Mentor Graphics) this is fully automatic, unless you specifically want to assign a given pin to a given signal. The "communication" between Synthesis tool and Schematic/PCB tool is automatic and requires no user intervention.
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    why do we need lay out based on VHDL

    Hi, Suppose you are a designer responsible for designing a schematic of some PCB. Suppose your schematic contains an FPGA... with something like 1200 pins... Now suppose that the guy that develops the VHDL for the FPGA... doesn't give you the full pin assignment until "five minutes" before you...
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    VHDL and State Machine and if..then... with no else

    VHDL and State Machine and if..then... with no else... and other code Styling Hi All, This is a post about GOOD/BAD coding style or even ACCEPTABLE code style. I hope to have (with YOUR contribution) some guidelines for avoiding some particular problems... that seems to be more common than...
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    Printing Variant Parameter o Assembly Drawing

    Dear All, I'm Using Altium Designer Winter 09 and I would like to print Assembly variants with a parameter set for each variant. I have tried the following: 1- Create a Project Parameter: Var_Value = "Dummy" 2- Created Several Variants: Var1; Var2; Var3 3- Setted the parameter Var_Value for...
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    UWB and distance measurements

    uwb distance measurement Hi ALL, I'm an hardware engineer from the digital world. I recently started working in UWB systems for distance measurements. Can you please help me to understand some basic concepts? 1- Do you know any (preferably free) good places to start understand UWB (specially...
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    Looking for some features on Altium Designer

    Hi all, I'm a newbie in Altium Designer. After working for many years with Orcad, and then with Mentor Expedition I now started with Altium. I found out that many features that I was used to are not present (or at leas I cannot find it ...) in Altium. Can you please tell me if the following...
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    Using TMS320C6415 for PCI master Transfers

    Hi, I have a PCI board that uses TMS320C6415 DSP for interface with the PCI. Does any one knows how can I use the DSP to perform a master transfer TO the Host PC. Thank you very much for your attention. AMCC
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    Problem coding FlipFlop in VHDL

    Dear Salma, Off course "end if" ... my "writing" mistake :-). A related question as raised in my head: What is the difference during for a synthesizer when coding a Flip-Flop with synchronous enable and reset of the two descriptions below? Description1: if(clk'event and clk = '1') then if...
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    Problem coding FlipFlop in VHDL

    Dear all, Thank you for your comments, but I think that the problem is not the initial value. 'run' WILL start '0' one way or another (either by default initialization or by the fact that en_aq is '0' initially (and this one is properly initialized). I wonder if there is any difference between...
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    Problem coding FlipFlop in VHDL

    en_aq Dear All, I'm using the following code for creating a FF with synchronous reset and enable: Run_Condition: PROCESS (aq_clk, en_aq, start, run) BEGIN if (aq_clk'event and aq_clk = '1') then if (en_aq = '0') then run <= '0'; elsif (start = '1')...
  11. A

    Problem with Initial State of FF on Xilinx

    Hi Avi, The reason because I care is that we_hd_r is a Write Enable of a FIFO that CANNOT be active during reset OR flags will go wild. (Thats what is currently happening). I can make some changes to the design to avoid the problem, BUT the main problem is: How do I know that this problem is...
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    Problem with Initial State of FF on Xilinx

    Hi All, I'm using HdlDesigner to describe a circuit for Xilinx Virtex-4, and I found something really strange. The problem is on the VHDL code bellow: if (aq_clk'event and aq_clk ='1') then we_hd <= st_nr_hd_a or st_nr_hd_b or st_rnd_hd_a or st_rnd_hd_b; we_hd_r <=...
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    Using PDT and QDMA on TMS320C64x

    Hi, Does any one knows if it is possible to use PDT on the QDMA channel on the TMS320C64x from TI? (I know that is possible on any of the other EDMA channels, but if using QDMA it is not clear on TI docs). Thank you very much in advance. AMCC
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    Question about the size of via

    Re: size of via ? Hi, Size o via is important. On trace signal they should be as small as possible to minimize inductance (that may cause signal slowing down or small glitches). (Answering Binu G: The vias are probably "microvias" typically from outer layer to first inner layer, typical size...
  15. A

    Ultra-High Precision Clock generator advices needed.

    Hi all, I need to have a programmable clock in the range of 100-300 Mhz with jitter bellow 1 ps (rms). My first solution is to use a VCO with a phase detector and frequency dviders. The proble is that, if I use a 1Ghz VCO i can only obtain 1GHz/N (N integer) or 250/200/166,67/142,86/125 and 111...
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