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Hi yjh106,
1. No, They are different.
DRV violations will bring timing issue when out of table at *.lib file enev if you have no timing violations.
verifyGeometry only perform short , spacing ...geometry check. No timing issue.
2. Could your check these error when using calibre or...
Hi
1. DRV means max transition, max cap, max fanout violation.
It's not the same meanings of the error flags of verifyGeometry.
2. Are your follow pins minimize width? Or probably be shifted with certain distance?
Hi Greatrebel,
I think the command is right, but I don't know why the calibre can recognize your top cell port "acc_out[0]".
Could you modify your port name from acc_out[0] to acc_out0 and run again to see if tool can't recognize brackets on top ? If the warning are still the same...
Hi Greatrebel,
Look likes you didn't put your label onto your top cell.
You can try it by adding following colume into your rule deck.
LAYOUT TEXT "acc_out[0]" 938.5 595 137 top_cell_name
or
LAYOUT TEXT "acc_out\[0\]" 938.5 595 137 top_cell_name
If still have warning, please...
Before routing, we need to correlate the delay calculator of APR(socfe) with signoff tool(primetime).
After routing, we need to correlate the RC extraction engine of APR(socfe) with signoff extraction tool(starRCXT)
First of all, you should get two files of std cells from your vendor : First, gds file to streamIn to your layout view(Laker) as a refenence library. Second, spice file to included in when doing LVS(calibre).
Using your P&R datebase to get final gds and streamIn to layout view with reference...
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