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Recent content by alokkmr18

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    Career guidance in VLSI having some experience

    hello sharath66 thnkx for ur valuable suggestion , can you give more information about vlsi .. so i will go for master in specific vlsi area after 2 year because itself in vlsi , there is so many field like frontend (FPGA design ,ASIC Design and verification engineer) and backend (STA,Physical...
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    Career guidance in VLSI having some experience

    I joined a start-up after my B.Tech in ECE as a verification engineer trainee. I want to get an MS in system on chip (SOC) or computer engineering after 2 years of experience. Is this a good decision or should I continue with my job? Why?
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    Frontend vlsi opening

    Hello everyone i am Btech graduate in electronic and communication in 2014 . Looking for frontend vlsi jobs , i know getting into vlsi as a fresher is not very easy and i am giving my best to search for job But not getting any result . I have applied to many vlsi company but they are not...
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    front end or RTL designer jobs

    hi , I m 4th year electronic and communication Btech student . I have strong knowledge of VHDL , Verilog , FPGA flow , ASIC flow and also familiar with different EDA tools . I have done two internship during my btech in VLSI and one paper publication in IEEE . I am interested to work in VLSI...
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    error in ncsim vhdl simulation

    when i m giving a command to testbench ncelab tst::follwoing error will occur ...plz help me out ..its urgent ncelab tst ncelab(64): 09.20-s009: (c) Copyright 1995-2009 Cadence Design Systems, Inc. include $CDS_INST_DIR/tools/inca/files/IEEE_pure/cds.lib | ncelab: *W,DLCPTH (./cds.lib,2)...
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    library during gate level simulation (netlsit file after synthesis)

    thanks for ur reply but i had done my synthesis of hdl design in design compiler (synopsys software) using all these library as u mention ... my ques is ..what are the library requires after the synthesis , when we go for post synthesis simulation in NCSIM simulator ... library are...
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    why we use IO pad for chip designing

    my ques : why we use io pad for designing , For chip designing , is it necessary to use IO pads , can't we go with our RTL design up to layout becoz i above mention in my previous post timing, Area & power with or without IO IO pad will increase these timing,Area & power factor...
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    why we use IO pad for chip designing

    actually ..i m working on ASIC design flow during my internship ...i designed RTL of time to digital converter in VHDL in ise(xilinx software) without using IO pads , then after simulation synthesis of rtl is done on DESIGN COMPiLER (synopsys) , where i get : slack (met) : 39998.21ns ...
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    library during gate level simulation (netlsit file after synthesis)

    what are the library requires when we go gate level simulation in NCSIM Simulator
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    why we use IO pad for chip designing

    hello every one... thanks in advance my ques : 1) why we use IO pads when we go for chip designing from RTL to LAyOUT level ... 2) why we use give single inputs to io pads & taking single output from IO pads.
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    Design comllier synthesis generated netlist simulation

    hello every one ... Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis. I m using Design comlier(synopsys) for synthesis of standard cells in VHDL. After doing successful synthesis it generates gate level netlist which i have to simulate to verify...
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    Which one is better for making career in ASIC design or FPGA designing

    thanks.... as told for verification purpose then ...which language vlsi company perfers , is it system verilog,vhdl ,verilog ... - - - Updated - - - if u can ...plz tell me the good books related for verification of design ..so i can learn early ....
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    meaning of post synthesis simulation

    what exactly meaning of post synthesis simulation ... right now ..my mentor told me do post synthesis simulation.. i dont why .. i have done my vhdl coding with their functional in modelsim software ..which is properly working ....after that i have done synthesis process in Design complier...
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    Which one is better for making career in ASIC design or FPGA designing

    if i choose ASIC designing ...then which knowledge should i have to acquire like ...digital design , VHDl , knowledge of software like synopsys,modelsim, ise(xilinx),soc encounter by cadence ...Floor planing and routing ..or i have to also concerate on digital signal processing (DSP) lilke...
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    Which one is better for making career in ASIC design or FPGA designing

    i have one query ...which one is good ASIC design OR FPGA designing ...becoz i am good at digital design with VHDL knoweldge and right now i am 3rd year btech student of electronic & comm. ..doing my summer internship in ASIC deign flow at VNIT nagpur VLSI lab as we know for ASIC design we...
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