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Recent content by Alka Arora

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    instansiation in VHDL function

    Hi, I have a multiplier in my VHDL function.Instead of using multiplier operator I want to instatiate the multiplier in a function.For example FUNCTION xyz(xxxxxxxxxxxx) RETURN STD_LOGIC IS ::: ::: VARIABLE mult : STD_LOGIC_VECTOR(LENGTH DOWNTO 0); BEGIN I want to replace ...
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    convert verilog to signed bit vector in verilog

    Hi, How can I convert integer type to signed bit vector in verilog? Thanks
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    verilog signed type conversion

    Thanks so much.I have a VHDL function FUNCTION "-" (L: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN RETURN - SIGNED(L); END; FUNCTION "ABs" (L: STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS BEGIN RETURN ABs (SIGNED(L)); END; I want to generate similiar logic in verilog...
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    verilog signed type conversion

    Hi , In VHDL we have a function to convert std_logic_vector to signed data type.Do we have anything like that in verilog to convert in to signed type in verilog. for example i have wire [8:0] diff; I want to convert it into absolute value. Thanks Alka
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    verilog parsing error

    Hi , The reg [5*64-1:0] worked.I still have to compare the results. Thanks
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    verilog parsing error

    It should be reg [5*64:0] or [5*63:0] ?
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    verilog parsing error

    I am getting "error: Multiple words referenced for memory Variable " in both the cases.
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    verilog parsing error

    Hi, Thanks.I get same error.I believe I need to make one signal of 5*64 .How Can I do that ?
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    verilog parsing error

    Hi , I am getting following error for this reg. reg [63:0] data_vec[0:4]; / Error: PARSE_ERROR: Parsing syntax error // Multiple words referenced for memory Variable 'data _vec' near token '(' How can I get rid of this error.How can I declare 5*64 bit vector? Thanks Alka
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    verilog error Multiple words referenced for memory Variable

    Hi, I have declared a reg as reg [63:0] data_vec[0:4]; I am getting parsing error Multiple words referenced for memory Variable How can I make one signal of 5*64 ,so that this error does not come? Thanks
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    verilog function to extend bits on left

    Hi, Could you please writing a verilog function to extend the bits in left. For example if a = 4'b1100; b = 5 The output should be out = extend ( a,b) should be equal to 01100; Thanks
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    convert vhdl function in to verilog function

    Hi , I need to convert this VHDL function in to verilog:Could you please help. -------------------------------------------------------------------------------------------------- FUNCTION EXT (ARGUMENT: STD_LOGIC_VECTOR; SIZE: NATURAL) RETURN STD_LOGIC_VECTOR IS VARIABLE RS...
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