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Recent content by alimassster

  1. alimassster

    FPGA implementation of SPIHT

    Hello friends I wonder if anybody could help me with an FPGA implementation of SPIHT algorithm thx in adv
  2. alimassster

    VHDL code for EZW & SPIHT image compression algorithms

    ezw vhdl Hello friends Does anybody have the VHDL source code for implementing EZW or SPIHT algorithms on FPGA? thx in adv
  3. alimassster

    bitstream by Xilinx system generator

    what is bitstream xilinx Thank you honey I'm going to present my seminar on thursday let's see what happens :D I'm going to master FPGA implementation techniques so it'll be very nice to be in touch with you . this is my Email address : alimassster@gmail.com Wish you the best take good care...
  4. alimassster

    a question about FIR parallel form implementation

    Thank you honey I'm going to present my seminar on thursday let's see what happens :D I wish you the best GOOD LUCK
  5. alimassster

    parallel and pipeline implementation of FIR

    are inputs stored in memory and fed simultaneously into MUL blocks OR as a stream , one by one , using BCIN-BCOUT ?
  6. alimassster

    bitstream by Xilinx system generator

    xilinx system generator memory echo47 I'm confused with a concept . I wonder if you can halp me . in virtex-4 sx55 DSP48 block , in order to implement a 64-tap FIR using 64 MUL block in parallel , are inputs stored in memory and then fed into multipliers simultaneously OR with a delay one...
  7. alimassster

    a question about FIR parallel form implementation

    Hello my friend that's not exactley a filter bank I'm just studying different implementations such as parallel & semi-parallel forms and the way they are put into hardware which is a Xilinx virtex-4 DSP48 device. I'm confused with the advantages of parallelism caz I see in parallel form inputs...
  8. alimassster

    parallel and pipeline implementation of FIR

    I think in the pipeline form after all the registers are full (which may takes some clk cycles) then there is an output in each clk am i right? my question is : are inputs fed into multipliers simultaneously or with a delay and one by one as a stream by using BCIN-BCOUT in DSP48 block(in Xilinx...
  9. alimassster

    bitstream by Xilinx system generator

    free version+xilinx system generator I asked that because of this part of UserGuide attached
  10. alimassster

    parallel and pipeline implementation of FIR

    Hi all I wanna know by cascading DSP48 blocks if we need for example N clocks to feed multipliers with N inputs in an N tap FIR filter to calculate Y , then what's the difference between the parallel form and a single MACC based form ( if there's an equal delay(number of clocks) in both forms)...
  11. alimassster

    FIR on FPGA(DSP48) an urgent question

    dsp48 fir filter thanks for your regard I just wanna know by cascading DSP48 blocks if we need for example N clocks to feed multipliers with N inputs in an N tap FIR filter to calculate Y , then what's the difference between the parallel form and a single MACC based form ( if there's an equal...
  12. alimassster

    FIR on FPGA(DSP48) an urgent question

    dsp48 Hello friends Imagine x as a continuous stream of input samples and y as a resulting stream the sample delay logic is denoted by Z^-1, where the -1 represents a single clock delay.The delayed input samples are supplied to one input of the multiplier.coefficients (denoted by h0 to...
  13. alimassster

    VHDL source code for EZW or SPIHT algorithms

    spiht vhdl Hello my friend Do you have any experience in implementing such these algorithms? I'd be thankful if you gimme a hand(any paper, matlab code,ebook , etc) thx in adv
  14. alimassster

    bitstream by Xilinx system generator

    xilinx bitstream Does SysGen produce a bitstream file to be downloaded in any FPGA If yes , how is it possible without place & route and so on? thx in adv
  15. alimassster

    a question about FIR parallel form implementation

    actualy I'm studying different implementations of FIR on FPGA Have you got any information about semi-parallel implementation? about Z^-1 delays : How the inputs should be stored and addressed to feed the multiply block? thx in adv
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