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op amp simulation
Then how should we actually simulate for whole system ( fully diff amp togather with the CMFB) if the CMFB is switch cap type? i read from this forum that we have to use spectreRF to simulate it, but how if the cadence tools i used do not have spectreRF license? Do we have...
hi guys,
Thanks a lot for your reply.
hi Allan_guo, could you explain further how MNN1 used for startup? and more detail explanation on MNN2 to reduce system error?
Initially i thought MNN2 is as startup circuit for this bandgap.
hi jianjing526,
nanch3 is native transistor and no...
hi all,
could anyone please explain to me the operation of the circuit below? i know this is a bandgap but i confuse for the part Q3, R and why there is a cap.
Q1=8Q2
Thanks a lot first. :D
another question is, what is the difference between model "nanch3" with "nch3" for TSMC .18u process?
I m using TSMC .18um process, currently simulate on a POR, the threshold voltage is around 1.214V. As the output POR will go in to some logic gates (DFF and inverter), so it is important to know whether this Vthreshold is able to let the logic regconized as logic "high" or not. I found online...
hi..
As what i understand, the POR block will be connected to some flops or other digital blocks, so the Vthreshold of POR block is important to make sure it will be higher than Vih of the digital circuit which connected to POR. Please correct me if i make mistakes.
i would like to ask, the...
worst cmrr
anyone could tell me is it anyway i able to get those scripts and test schematic in the white paper " Functional Verification Of A Differential Operational Amplifier" ??
thanks in advance
how to reduce offset
i have an op-amp which is used for LDO. the Vref is about 1.16V.
At that point, my op-amp's offset is ~6mV will this a problem for my LDO?
How to lower the op-amp offset? my op-amp is only one stage op-amp which using high swing cascode current mirror as load current...
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