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Thanks for your reply. Wont there be any academic or web trial versions of those expensive tools? For now, this is for learning/hobby purpose so I wont mind a ***** or a trial version.
Do you know if there is a formal learning resource for board design?
Hi
I am an Electronics Engineer and have vast experience in FPGA design with Xilinx and Altera FPGAs. Now I want to extend my expertise by learning board design. By the way, I have a Zybo board and I have schematic as well that I found on digilant website...
Hi everybody,
I want to use the Altera's PCIE core in a project. I have red the basics of transaction protocol. I want to know about the indication that tells the link training is completed by the physical layer and now i can send mem read/write requests TLPs. I mean, is there any register in...
I am using scrambler / Descrambler with FEC for block synchronization in the following manner
Blocks---->FEC Encoder----->Scrambler-------Channel(+err)-------block synchronizer------>Descrambler---->FEC-Decoder--->Blocks
I am using a Burst error correcting cyclic code for this purpose with...
If you are starting to learn some testbench skills, try system verilog for making testbenches. here is the book from you can start on.. Assertion-Based Design
Re: leading one detector
One method similar to the method posted by permute is present in Altera's cookbook in the section of bit scan methods. But I think, the method posted by permute is a bit better, since it uses adder rather than subtractor and saves a LUT
Re: leading one detector
I have only a cycle to decode it completely
---------- Post added at 11:55 ---------- Previous post was at 11:51 ----------
i have only a clock cycle and the input is 66-bits wide.....
splitting the decoder my help in increase fmax but this will no decrease the...
I need leading one detector which can detect the leading one and tells the position of first '1' i.e.
i/p 00000000111100000000
o/p 00000000100000000000 = 9
one way in my mind was to use a priority decoder(using casex or series of if..else)
but that uses much resource for larger...
You can use synchronizer circuits to sync read and write pointers, these are usually simple series of flops(usually 2 flops). To measure depth of a cyclic buffer or FIFO you can refer wikipedia for upto four techniques through which you can measure depth or FULL and EMPTY conditions. You can...
why are you going for an FPGA kit in order to learn FPGA???? simulators like Modelsim and many other are powerful enough to model your verilog/VHDL code like real hardware. Even though, many of professional fpga engineers dont need a hardware setup to verify their module's functionality...
let you are converting a data bus 10bits wide to a data bus 15bits wide.
reg [9:0] bus_a; //bit10 is sign bit
reg [14:0] bus_b;
always @(*)
bus_b = {bus_a[9],bus_a[9],bus_a[9],bus_a[9],bus_a[9],bus_a[9], bus_a[8:0]};
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