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Recent content by ali_bukhari

  1. A

    serial to parallel conversion code in verilog

    but i m using on board system clk of 16 mhz clk this has solved my problems thx 4 ur reply . n do teeme if in any i might help u out
  2. A

    Looking for info about FSM and ASM

    fsm & asm i kw their abbreviations i wan to kw the detail of each one of them
  3. A

    Looking for info about FSM and ASM

    any idea abt fsm and asm?
  4. A

    serial to parallel conversion code in verilog

    do u ve any idea of fsm if i send u the fsm code written in verilog would u b able to errect it 4 me?
  5. A

    help needed in fsm verilog code

    i ve written a verilog coge for decoding manchester bits which are incapsulated in between sync bits and a parity bit ,i ve written this code using fsm can some 1 remove the logical error or temme why states r nt working?
  6. A

    serial to parallel conversion code in verilog

    so nice of u kindly lemme kw is it possible to make exact clks of 2 mhz n 8 mhz from 50 mhz system clk ; so that they are synchronized as well Added after 2 minutes: do u ve any experience of working on embedded systems?
  7. A

    serial to parallel conversion code in verilog

    thx 4 ur reply wud u temme exactly the name of the writer of htis book
  8. A

    serial to parallel conversion code in verilog

    anyone who can send me the verilog code for serial to parallel conversion
  9. A

    manchester decoder in verilog

    anyne who can send me verilog code for manchester decoder do repyly me on my email id leo_second2none@hotmail.com
  10. A

    1553 decoder implementation on fpga

    i want to decode 1553 for this i want to creat clks of 2 mhz and 8 mhz from system clk of 50 mhz ( the oscillator on spartan 3 fpga board) any one who cud help me with this........,,,,,,,,,,,????????
  11. A

    i want verilog xpert to help in manchester decoding

    i m working on final term project ; i want to decode the 1553 manchester encoded data ; using verilog hdl ; any1 who can suggest somthing or help me in writting verilog code plz do reply
  12. A

    verilog code for dpll for manchester decoding

    i need to a verilog code for dpll(digital phase lock loop) inorder to implement decoder for 1553 b bus can sm1 help me with this
  13. A

    i need verilog code for manchester decoder on fpga

    i m workin on my final term project ,i need to implement 1553 bus interface card on fpga , i have done with the encoder part of it and now workin on decoder , can sm1 help me for the logic , or even the verilog code for the decoder .
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