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Recent content by alard

  1. A

    How to design a CML RS-latch?

    Could anyone tell me how to design a basic CML RS-latch (no enable input needed). Thx in advance
  2. A

    question about the transmission gate

    thx for both of you~~~
  3. A

    question about the transmission gate

    Hi, Usually how to decide the size? In addition, is it needed to make the PMos transistor three times lager than the nmos due to the different mobility? Best Regards, Jian
  4. A

    How to design a voltage depend on temperature and Vcc

    voltage depend on Hi I need a voltage of 2.5V at room temperature(27°, Vcc=3.2V), which required to be rise accordingly with Vbe(roughly 2.7V at 120 degrees). In addition, it should also increase with the same amount (300mV) if Vcc raised to be 3.5V. Could anyone provide any suggestion...
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    parameter in SpectreMDL

    spectremdl ocean Hi, I 'd like to vary a parameter which is already defined in the netlist. What I want to do is to first simulate with an initial value. Then calculate an optimal value and simulate the second time with this one. Could anyone tell me how to do it? P.S. What is the difference...
  6. A

    Cadence - file of transient simulation is too big

    Try to use 'select' wherever it is possible in the save all options, then use Outpus --> to be saved.. to choose the ports that you are going to plot
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    Anybody know SpectreMDL?

    spectremdl time Hi, I 'd like to vary a parameter which is already defined in the netlist. What I want to do is to first simulate with an initial value. Then calculate an optimal value and simulate the second time with this one. Could anyone tell me how to do it?
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    Where to find the functions can be used in spectre MDL?

    Hello, I read the spectre MDL user guide and reference. In the turorial there are some predefined functions like max(), deltax(), risetime() and so on. The question is where can I find the rest ? THX in advance
  9. A

    bias circuitry for current steering DAC

    hi all I am doing 12 bits DAC with classical segmented current steering structure. Totally I have 40 bipolar cascode current cells. Could anyone suggest me how to design the bias circuitry to bias these current sources? How should I divide them into several groups and what kind of current...
  10. A

    how to set equal time step of transient simulation in Cadenc

    thx a lot
  11. A

    how to set equal time step of transient simulation in Cadenc

    Hello, The problem is as follows, When I put 10ps for the maxstep in the option of transient simulation, I saw some steps running at 6 or 7 ps. When I set both step and maxstep to 5ps, then the simulator run at 2 ps for some step. Finally I tried with 1ps, then 50as appears.... How could...
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    How to simulate the SFDR of an ideal 12-bit DAC?

    Hello, I have a question about the use of DFT in cadence. My 12-bit DAC has the sampling frequency 1.5Ghz. I use an ideal 12bit ADC to generate the input signal of DAC. My target is to find the SFDR of 2 frequencies(any) between 0-750MHz. So the questions are 1. how should I choose this...
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    Does cadence(5141 in my case) support vectors in verilogA?

    Hello Juven, Thank you for you reply. As far as I know, 'genvar' is not supported in cadence(5141).
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    Does cadence(5141 in my case) support vectors in verilogA?

    veriloga genvar not supported Hello, I wrote a short code to simply handle my input signal. It can pass the compilation but the output waveform is really strange. If I don't use vector but list all the ports one by one, it works which means the code itself functions well. In addition, I also...
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    [SOLVED] Region Defination of BJT in cadence?

    Hello DenisMark, I just found related info as follows, region=fwd Estimated operating region. Possible values are off, fwd, rev, sat, or breakdown I still don't know how it is corresponed to the numbers that cadence shows me.
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