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Recent content by alanray

  1. A

    how to synchronization domain clk and asynchronous signal ?

    how double synchronization works in sung group there are some good reference for async design
  2. A

    what does the word 'IPO' stand for?

    Use magma , it will do the IPO for you
  3. A

    $cl linux - file to download

    Thand you!
  4. A

    Writing the USB stimulus. Does anybody used VERA ?

    you can use synopsys smartmodel
  5. A

    FASTSCAN and 2 clock domains

    2 clock domain shift clock use latch to pass differnet clock domain
  6. A

    Error message in Synopsys DFT after check_test

    TESTCLK GEN Did your design have internal gate clock
  7. A

    Does IC50 support se ?

    no
  8. A

    estimate clock tree delay

    I think you should gen clock tree in the backend tool, and then you gen sdf file , then you can check the phycial delay of two clock, and then you can modify diffenrent clock domain phase, this is call ipo.
  9. A

    N*anosim on Linux - ftp links

    How can i get the link, pls share it to me.
  10. A

    N*anosim on Linux - ftp links

    there are no this directory
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