Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I've only found one method, use fully-diff op, neg-input with delay-connect, and pos-input with delay-free-connect and phase reverse.
Can anayone tell if this will make some thd on the output?
Or can anayone give me some other method?
3.3v vdd
presim ac and cmfb are both ok
ac gain=75dB
cmfb gain=70dB
dc operation node OK cm-output=1.65v
but when do c-only postsim
gain is still large
ac=73dB
cmfb=65dB
but cm output voltage is 1.5v!
why?
the op is p-input pair single stage
cmfb connect to p-load of the cascode op
if only for cap-load, you can use 1-stage folded-cascode architecture, if you need large dc gain, you can add gain-boosting to it.
300nF load, 100kHz bandwidth, gm~200mS
sr=5v/ms, so tail current~1.5mA
need large current and large w/l for input pair.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.