Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
ADPLL Design in VHDL
Hi
can You help me ?
I have designed a PLL in VHDL(test bench and UUT in Attachement).
It run With M=16, K=8, N=8 but only small change
of u1 and it go out of lock. What is the reason ?
I try all possible combinations of M,K,N but without success ?
Thank You in advance. Anton
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
