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Recent content by aiko89

  1. A

    How to put the reg value in this color LCD controller code?

    Color LCD controller module Lab1 ( Input DCLK_50, // 50 MHz Input iKEY, // Pushbutton[3:0] Input iSW, // Toggle Switch[17:0] Output [7:0] LCM_DATA,LCM_HSYNC,LCM_VSYNC,LCM_GRST,LCM_SHDB,LCM_DCLK ); // LCM_DCLK is 50MHz, LCM_SHDB(logic 1) reg [ ] H_Count; reg [ ] V_Count; reg [ ] Mod_Cnt; reg [...
  2. A

    help me with this pin planner!! I cannot assign it..

    module music( input wire nrst, //reset signal input wire clk, //source clock 5Mhz output reg [3:0]note, //index of musical note currently being played output wire speak //sound enable ); //enable sound if current note is not zero index assign speak = (note !=0)...
  3. A

    I want to make sound with DE2 and Verilog HELP ME

    Hi guys ! I have a school project with DE2 board & Verilog code, and we're going to make something like a sound generating machine. It is kind of JUKE BOX. First of all, I want to make single tone sound, like beep sound. For Example, when I push KEY 1 , DE2 board sounds (like beep!) To make...
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    TCL tutorial or example to write testbench for VHDL code

    Re: fpga testbench tcl module count (clk, rst, enable, cnt); input clk, rst, enable; output [3:0] cnt; reg [3:0] cnt; always @(posedge clk or posedge rst) // async active high reset begin if(rst) cnt <= 0; else if(enable) cnt <= cnt + 1; end endmodule...
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    Verilog code error: unable to determine top module

    Re: verilog first code hi anyone there can help...i need your testbench... thank you
  6. A

    Verilog code error: unable to determine top module

    Re: verilog first code may i know that ur code that have a testbench.. i needed to do for my counter.... hope that ue can help mie... thank you advance....
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