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Recent content by ahmad898

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    Calculating the reliability of PUF instance

    Dear all, I have an Arbiter PUF with reliability of 99.58%. Suppose I have 256 input to the PUF which generates 256 responses as an output. Now, I want to replace the 50% of input bits with 50% of response bits, randomly. In fact, I create a feedback loop between the output and input of the...
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    Do we need to check hold time violation between synchronizing flip-flops?

    Thanks for your reply. I have already run timing analysis and I get the hold violation for the sync flops. So, here is the bottleneck. If I dont constraint such paths the tool will probably put some buffers between them when running optimization in P&R. I can put constraint on these paths with...
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    Do we need to check hold time violation between synchronizing flip-flops?

    Yes I want to aviod inserting buffer between synchronizer flip-flops as it reduces the MTBF.
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    Do we need to check hold time violation between synchronizing flip-flops?

    I have two-stage synchronizing strcuture consisting of two flip-flops. My question is that do we need to check hold time violation between flip-flops of synchronizer. Somewhere I read that these two flip-flops should be close together as much as possible and somewhere else I found that between...
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    [SOLVED] Hold time calculation for single Flip-flop

    Thanks for your reply. I follow your suggestion, remove clock uncertainty and add the following constraints instead. set_clock_latency 3 -source -early -dynamic 0.5 [get_clocks clk] set_clock_latency 5 -source -late -dynamic 0.5 [get_clocks clk] I expect to see the dynamic part in setup...
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    Do we need set_clock_uncertainty in post-layout timing analysis?

    I know that set_clock_uncertainty is for taking the clock skew and jitter into account during pre-layout timing analysis. But, after post P&R we have a propagated clock where the skew is known. My question is that if I put the set_clock_uncertainty contraint in sdc for post P&R STA, does it...
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    [SOLVED] Hold time calculation for single Flip-flop

    I have already enabled the clock reconvergence pessimism in PT using the following commands. set_app_var timing_remove_clock_reconvergence_pessimism true, and the results are the same. I will post the schematic and the report generated by PT, where the hold timing violation occurs. 1677411643...
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    [SOLVED] Hold time calculation for single Flip-flop

    OK, I have an interesting question. Suppose you have a single flip-flop, where its input (D) comes from a combinational logic driven by its output (Q). In my opinion, the hold time violation in this case does not relate to clock skew or jitter at all, as we are inspecting the violation for that...
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    Mismatch between SPEF file generated by StarRC and the verilog netlist

    Thanks for your replay rca. I have another question. Is it possible to import the spef file generated by third-party tools and import it to innovus using spfIn or read_parasitics commands to aviod updating RC scale factors. In my opinion, we have two options here, one is to update the RC scale...
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    The net has dangling wire

    Yes that's right. This violation eventually got resolved at the final stages of routing. It is like some kinds of warning to the user that some VDD and VSS nets are floated.
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    The net has dangling wire

    I am begin to learn more about design with macros in innovus. I place the macro, design power grids and straps, and finally Srout the core power rings. But, at the boundry of the macro the core rings face the problem of dangling wire as you can see in the below image. My question is that how...
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    Calibre PEX netlist has port names with uppercase letter

    It is weird since I already added PEX NETLIST UPPERCASE KEYWORDS NO to the enviorment variables and the output of Calibre is the same and all nets are in uppercase.
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    Calibre PEX netlist has port names with uppercase letter

    Ok I finally managed to extract the pex netlist out of calibre that matches with my verilog netlist. But, there is still one poblem. The netlist extracted from pex in spef format has changed port names with uppercase letter and this leads to the mismatch error in primeTime. My question is that...
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    Mismatch between SPEF file generated by StarRC and the verilog netlist

    Thats a good idea. I was faced with this issue in PT when used the ECO given by the PT without P&R information. I didnot know that we can import DEF file to the PT to select the position of modified or added cells. I should try this. Thanks for this guide.
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    Mismatch between SPEF file generated by StarRC and the verilog netlist

    The StarRC or the calibre pex is defined by foundry for sign-off. So, based on your answer, the qrc tech file is not enough for accurate sign-off using Quantus and the scaling factor should be provided by comparing spef file with the calibre or StarRC. Is that right? Also the innovus has the...
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