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I am not using the exponent option, the block produce two 32 bits output (real and imaginary) and I made a component that will take this two words and calculate the complex number magnitude. The output of this component is the result I am using to detect the power of each frequency bin.
I actually succeded solving the problem some days ago. The problem was that the FFT block needs to get signed input data while the ADC I am using is producing unsigned data results. So I converted the ADC output word to become a signed data and it all worked out pretty well.
Thanks anyway ;-)
I am inputing a sinus wave into an ADC, the ADC is ploting 16bit data that is tranformed to the FFT core of the altera (8192 samples). The outputs of the FFT component are getting into mul_adder (real*real+imag*imag) and the into a sqrt mega wizard, I take the q output of the sqrt component as...
But if I am using PLL with seperate VCO I can't use muting (which enables locking at the same time) so I'll need to use only one synthesizer circuit or I'll have alot noise at this area. Also one VCO that generates fundemental frequencies according to my needs is unavailable, or that it will be...
Yes I figured it after writing the last post, it seems to be usefull if I will decide to use it at this operation. I am also trying to find two different synthesizer that will be able to do the same and be specified to work at narrower range of frequencies so they won't use VCO output divider...
Well the SPI really doesn't that affective. Even if it is I really want to focus on eliminating the spur signals at this range of frequencies.
I know that the ADF 4350 has fastlock switch but I'm not so sure about its spur performances, on the other hand the LT part should have great spur...
All of the plls/synthesizers are using serial interface. My project will probably work at 136MHz clock so it won't hurt the lock time too much. The problem is the loop filter. As much as I know in order to get better phase noise performances I need to use smaller bandwidth loop filter - the...
This LO generator should be connected to a mixer that will downconvert the RF input. After the downconversion there will be an IF filter so that I will be able to sample it with ADC and have a resolution of about 67kHz. I don't know exactly which spurs appearnce is better in this application but...
Hello,
I am trying to develop a synthesizer that will supply changeable LO signal between 950MHz to 2300MHz or at least between 950MHz to 2070MHz. I need this synthesizer to achieve frequency lock as fast as possible, let's say 500uS maximum.
From what I found in order to achieve this wide range...
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