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divide by 2 counter
signal q : std_logic_vector(1 downto 0);
................
begin
process(clk_i,reset)
begin
if (reset = '0') then
q <="00";
elsif (clk_i'event and clk_i = '1') then
q <=q+1;
end if;
end process ;
clk_div2 <= q(0);
clk_div4 <= q(1);
dual clock counter
hi,
about the flag
you need two negative edge D-FF with asynchronous reset
D-FF1:D<->'1',CLK<->I_UP,/RESET<->I_DOWN
D-FF2:D<->'1',CLK<->I_DOWN,/RESET<->I_UP
and then
up_down_flag<=Q1 AND NOT Q2;
Re: dual clock counter
hi,
you can try that
add internal node
signal up_down_clk:std_logic;
signal up_down_flag:std_logic;
then
up_down_clk<=I_UP AND I_DOWN;
up_down_flag<=...............................
process(up_down_clk,I_CLR,I_LOAD_N,up_down_flag)
begin
if (I_CLR='1') then...
hi,
what does 8254 parameter tCL mean?
can we set lock command or read back to latch count
at period of tCL min~max?
what is the structure of OL(output latch),does it synchr to clk?
thanks
avalon nios2
hi,
i have completed a simple test of 8 bit output port (Custom Peripherals)
and embedded in NIOS2 system
how to access it by NIOS2 IDE C
thanks
hi budhy
I have another question between (prgram mode) and (5V chip erase mode).
from following table the /CE,/OE,/WE,Ai of two mode are the same.
how does it to recognize (prgram mode) or (5V chip erase mode)
thanks
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