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Recent content by 20tech11

  1. 20tech11

    PSPICE Model for ADL5391

    Hi, Has anyone got a PSPICE model for ADL5391? Could you please share the same? Many Thanks
  2. 20tech11

    [SOLVED] OP Amp biasing question

    I would suspect the offset present at the input. For the transistors in quiescent state and offset cancelled circuit the output DC voltage should be at midpoint the power supply, which will enable us to provide maximum output swing.
  3. 20tech11

    [SOLVED] OP Amp biasing question

    Hi, But i doubt as the CMOS non-inverting input (floating input) should have a noise voltage which provides Vgs -Vth such that the input transistor should be turned ON. Otherwise no current flow will be there in the circuit. Similarly the Vin on the inverting terminal could be a small signal...
  4. 20tech11

    interupt 0 on pic18f4620

    I would suggest you to look at Microchip site, where you can get a number of examples!!. You have to configure USART Tx & Rx interrupts. You should also configure correct baud rate.
  5. 20tech11

    interupt 0 on pic18f4620

    Have you enabled TMRxIE ( Timer0 Interrrupt)?
  6. 20tech11

    [SOLVED] OP Amp biasing question

    As the transistors are not biased they are not at all in saturation and shouldn't get any output.
  7. 20tech11

    Hi gh frequency Analog multiplication

    I have seen ADL5391. But Im looking some other manufacturer too..Can you people suggest some? Many Thanks
  8. 20tech11

    Hi gh frequency Analog multiplication

    Hi , Has anyone used any high frequency ( DC to 1GHz) multiplier for some application? Could you please tell me some ICs that will do the same job? Many Thanks
  9. 20tech11

    Cadence virtuoso layout editor

    Yeah actually if we use DIVA for DRC running then from the same tab ie verify ->markers-> delete all will turn off the DRC error highlights... and if we use Assura same is done by close ELW on the File menu of error layer window..
  10. 20tech11

    IC Layout:- Running LVS

    Hi All, I have a basic doubt may be it is stupid. I am working with the design of a 8 bit DAC and for better matching I have to follow common centroid geometry and have to add dummy elements. But when we run LVS will these dummy elements be considered as extra instances and Will the LVS show...
  11. 20tech11

    current mirror matching of DAC

    Hi erkl, Thank you very much..This is absolutely clear...Thanks for your help..
  12. 20tech11

    current mirror matching of DAC

    This is the simplest DAC one can see and it is having its own problem. I am using this, to be familiar with Layout. Here the transistor size ratio are 32 , 16, 8, 4 , 2 ,1 and the transistor having the large size carries the bias current and ofcourse that determines the bias voltage. All other...
  13. 20tech11

    Cadence virtuoso layout editor

    @jgk2004 but I couldn't see such an option, may be I am just in to the lay out!! @Jimito12 But I used the normal DIVA rules for running the DRC and not using the Assura now..
  14. 20tech11

    current mirror matching of DAC

    LSB carries 15 uA.. and the bias curret is 32*15uA. So I have a total of 63 transistors in my circuit. I am little confused now.Waht is the difference between DAC transistors and current mirror transistors according to you?

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