Zynq zc702(Creating a First IP Integrator Design) using Xilinx 14.3 Planahead???

[kaiserschmarren87]

Zynq zc702(Creating a First IP Integrator Design) PS part not clear..

QUESTION Regarding PS Part:
Hello,

I am new to Zynq(PS+PL) system and Vivado tool. In my project I have to use Xilinx ISE 14.3 with Zynq zc702 evaluation board. I have to work on using PlanAhead and XPS for this.

I am trying to test the sample project from 'The Zynq Book' - Source Tutorial example project to blink LED. I can get the PL - Programmable Logic part but not the PS - Processing System part. I am reading The Zynq Book and Zynq 7000 user guide. In simple terms can anybody explain the use of PS part while designing a system?

In this push button and LED using AXI GPIO example, how the data flows?





The zynq book source tutorial: **broken link removed**


I have another question:

To implement the following data flow do I need External AXI Master and Slave connector?

Push_Button -> AXI GPIO -> AXI Interconnect(1) -> AXI External Slave Connector -> FSM Logic to test the push button pressed or not and make LED glow -> AXI External Slave Connector -> AXI Interconnect(1) -> AXI GPIO -> LED

 

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The Zynq PS is an ARM processor subsystem (i.e. it's a hard IP ARM Cortex).

The AXI master in the Zynq book is the ARM. In your data flow it would be the FSM, which would have to have an AXI master interface to control both AXI slaves. You would have to package that IP into an IP integrator repository to use it in an IP integrator flow. See this document starting on page 14 "Using the Create and Package IP Wizard for AXI IP".