Zynq : peripheral request interface (DMA sync) logic interface in PL side

[wille72]

Hello,

I'm using ZC706 board. We are planning to use PS side DMAC controller and AXI GP interface(s) to communicated with PL side IP/logic. I would like to know if there is any IPs in Vivado 2013.2 to deal with peripheral request interface signalling in PL side? I couldn't find such logic in AXI Interconnect IP.

Regards,
Ville-Veikko

 

[wille72]

Hello,

I'm using ZC706 board. We are planning to use PS side DMAC controller and AXI GP interface(s) to communicated with PL side IP/logic. I would like to know if there is any IPs in Vivado 2013.2 to deal with peripheral request interface signalling in PL side? I couldn't find such logic in AXI Interconnect IP.

Regards,
Ville-Veikko

Actually this peripheral request interface is not needed at all. AXI flow control with interrupts is enough.

Ville-Veikko