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ZL30251 phase aligned

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I just want to confirm whether the part zl30251 has phase aligned outputs? If not, can it be aligned?

Also, can you confirm whether both the clock outputs are LVCMOS?

Can you please help me with this?

I want one clock output to be 12.8MHz and the other clock output to be two the frequency of the first clock, i.e, 25.6MHz.
The datasheet mentions that the clock output can be phase aligned. But if the clock outputs are two different frequencies, how can the clock outputs be phase aligned?

Can you help me?
 

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Sure, outputs with integer frequency output can be phase aligned. E.g. 0 phase means each second rising edge of the 25.6 MHz output coincides with each rising edge of the 12.8 MHz output.
 

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Sure, outputs with integer frequency output can be phase aligned. E.g. 0 phase means each second rising edge of the 25.6 MHz output coincides with each rising edge of the 12.8 MHz output.
Thank you very much for your answer.

So, since the output clocks are integer multiples, I can get them phase aligned right? As mentioned in the datasheet, with the help of the PACR1 and PACR2 registers, I can get the outputs to be phase aligned right?

Also, the outputs are LVCMOS only, right, as mentioned on top of page 7?
 

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Each configurable as 2xLVCMOS or 1xCML (can support e.g. LVDS), as clearly stated in the datasheet.
--- Updated ---

Each configurable as 2xLVCMOS or 1xCML (can support e.g. LVDS), as clearly stated in the datasheet.
 

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