zero wire load model - what are all information it gives?

[jitendravlsi]

zero wire load model

Dear ALL

BEFORE STARTING THE DESIGN WE CHECK TIMING CONSTRANTS BY USING:

"timeDesign" command

it uses zwlm(zero wire load model)

please tell me from where we get this zwlm and what are all the information it contains?

regards
jeet

 

[arjun1110]

Re: zero wire load model

Hi Jitendra,

>>please tell me from where we get this zwlm and what are all the information it contains?

Wireload model is something which calculates the net delay based on the fanout of a particular gate. Basically its a statistical based model which gives the prelayout estimation. Wire load model information will be in the liberty files(what we call dotlibs) provided by foundary.

library(myWLM) {

/* zero wire-load */
wire_load("zero") {
resistance : 0;
capacitance : 0;
area : 1;
slope : 1;
fanout_length(1,2000);
}
}

library(2K_6LM) {
wire_load("2K_6LM") {
resistance : 1.2;
capacitance : 0.2;
area : 1;
slope : 1;
fanout_length(1,2000);
fanout_length(2,2500);
fanout_length(3,3000);
fanout_length(4,4000);
fanout_length(5,5000);
fanout_length(6,6000);
fanout_length(7,7000);
fanout_length(6,8000);
}
}

Regards,

 

[jitendravlsi]

Re: zero wire load model - what are all information it gives

thanks Arjun,

I was aware of wlm in .lib file but I wanted to clear about zwlm.

 

[Chethan]

Re: zero wire load model - what are all information it gives

Hi,

All the wire load models in the Synopsys liberty files(.LIB files) are given by the foundry to the Std cell IP development company. These companies after doing characterization append this wireload model information into the .LIB files. The wireload models are given for different load conditions including zero load. These wireload models are just a rough estimate of the load that can be caused by wires.

regards
Chethan