Zero delay for clock tree buffers/inverters in timing report

[useless_skew]

Please have a look at the timing report generated using SoC encounter.

The post CTS report shows zero delay for clock tree buffers/inverters.
Why is that so?

Thanks.

 

[iwpia50s]

Timing report

Looks like the clock is not propagated.

 

[useless_skew]

Re: Timing report

Yes iwpia50s... The clock was not propagated.

Thanks,
Useless_skew

 

[sam536]

Re: Timing report

I dont have experience in SOC encounter. After CTS, the clocks need to set as propagated clocks in Synopsys tools. Like, Set_propagated_clock [all_clocks]. Check the same in SOC encounter also. If you have some ting like, Ideal net attributes on clock related cells, try to remove it and check timing report.

To find out the reason in synopsys tools, we have command called, report_delay_calculation -from <> -to <> to cell. Which will show the reason for Zero delay or wrong delay calculation. Check the same in SOC encounter. Check the attributes on the clock network.

Regards,
Sam

 

[arunragavan]

Timing report

please get whether ideal_network applied on clk port..?